1 <?xml version="1.0" encoding="UTF-8"?>
\r
2 <architecture xmlns="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE"
\r
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
\r
4 xsi:schemaLocation="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE
\r
5 http://www.tik.ee.ethz.ch/~shapes/schema/architecture.xsd"
\r
8 <!-- rdt(tile_0) arm subsystem -->
\r
9 <processor name="tile_0.arm" type="RISC">
\r
12 <memory name="tile_0.rdm" type="RAM">
\r
15 <hw_channel name="tile_0.armbus" type="BUS">
\r
16 <configuration name="frequency" value="100000000"/>
\r
17 <configuration name="bytespercycle" value="1"/>
\r
20 <!-- rdt(tile_0) magic subsystem -->
\r
21 <processor name="tile_0.magic" type="DSP">
\r
24 <memory name="tile_0.ddm" type="RAM">
\r
27 <hw_channel name="tile_0.magicbus" type="BUS">
\r
28 <configuration name="frequency" value="100000000"/>
\r
29 <configuration name="bytespercycle" value="1"/>
\r
32 <hw_channel name="tile_0.dma" type="DMA">
\r
33 <configuration name="frequency" value="100000000"/>
\r
34 <configuration name="bytespercycle" value="1"/>
\r
37 <!-- rdt(tile_0) distributed external memory -->
\r
38 <memory name="tile_0.dxm" type="DXM">
\r
41 <!-- rdt(tile_0) ahb multi-layer bus -->
\r
42 <hw_channel name="tile_0.ahb0" type="BUS">
\r
43 <configuration name="frequency" value="100000000"/>
\r
44 <configuration name="bytespercycle" value="1"/>
\r
47 <hw_channel name="tile_0.ahb1" type="BUS">
\r
48 <configuration name="frequency" value="100000000"/>
\r
49 <configuration name="bytespercycle" value="1"/>
\r
52 <!-- rdt(tile_0) dnp -->
\r
53 <hw_channel name="tile_0.dnp" type="SPI">
\r
54 <configuration name="frequency" value="100000000"/>
\r
55 <configuration name="bytespercycle" value="1"/>
\r
58 <!-- rdt(tile_0) on-tile communication paths -->
\r
59 <!-- rdt(tile_0) arm paths via dxm-->
\r
60 <writepath name="tile_0.rdmtodxm">
\r
61 <processor name="tile_0.arm"/>
\r
62 <txbuf name="tile_0.rdm"/>
\r
63 <hw_channel name="tile_0.armbus"/>
\r
64 <hw_channel name="tile_0.ahb1"/>
\r
65 <chbuf name="tile_0.dxm"/>
\r
66 <configuration name="delay" value="0"/>
\r
67 <configuration name="cycles" value="8"/>
\r
70 <readpath name="tile_0.rdmfromdxm">
\r
71 <processor name="tile_0.arm"/>
\r
72 <chbuf name="tile_0.dxm"/>
\r
73 <hw_channel name="tile_0.ahb1"/>
\r
74 <hw_channel name="tile_0.armbus"/>
\r
75 <rxbuf name="tile_0.rdm"/>
\r
76 <configuration name="delay" value="0"/>
\r
77 <configuration name="cycles" value="8"/>
\r
80 <!-- rdt(tile_0) arm paths via rdm-->
\r
81 <writepath name="tile_0.rdmtordm">
\r
82 <processor name="tile_0.arm"/>
\r
83 <txbuf name="tile_0.rdm"/>
\r
84 <hw_channel name="tile_0.armbus"/>
\r
85 <chbuf name="tile_0.rdm"/>
\r
86 <configuration name="delay" value="0"/>
\r
87 <configuration name="cycles" value="8"/>
\r
90 <readpath name="tile_0.rdmfromrdm">
\r
91 <processor name="tile_0.arm"/>
\r
92 <chbuf name="tile_0.rdm"/>
\r
93 <hw_channel name="tile_0.armbus"/>
\r
94 <rxbuf name="tile_0.rdm"/>
\r
95 <configuration name="delay" value="0"/>
\r
96 <configuration name="cycles" value="8"/>
\r
99 <!-- rdt(tile_0) magic paths via ddm-->
\r
100 <writepath name="tile_0.ddmtoddm">
\r
101 <processor name="tile_0.magic"/>
\r
102 <txbuf name="tile_0.ddm"/>
\r
103 <hw_channel name="tile_0.magicbus"/>
\r
104 <chbuf name="tile_0.ddm"/>
\r
105 <configuration name="delay" value="0"/>
\r
106 <configuration name="cycles" value="8"/>
\r
109 <readpath name="tile_0.ddmfromddm">
\r
110 <processor name="tile_0.magic"/>
\r
111 <chbuf name="tile_0.ddm"/>
\r
112 <hw_channel name="tile_0.magicbus"/>
\r
113 <rxbuf name="tile_0.ddm"/>
\r
114 <configuration name="delay" value="0"/>
\r
115 <configuration name="cycles" value="8"/>
\r
118 <!-- rdt(tile_0) magic paths via dxm-->
\r
119 <writepath name="tile_0.ddmtodxm">
\r
120 <processor name="tile_0.magic"/>
\r
121 <txbuf name="tile_0.ddm"/>
\r
122 <hw_channel name="tile_0.dma"/>
\r
123 <hw_channel name="tile_0.ahb1"/>
\r
124 <chbuf name="tile_0.dxm"/>
\r
125 <configuration name="delay" value="0"/>
\r
126 <configuration name="cycles" value="8"/>
\r
129 <readpath name="tile_0.ddmfromdxm">
\r
130 <processor name="tile_0.magic"/>
\r
131 <chbuf name="tile_0.dxm"/>
\r
132 <hw_channel name="tile_0.ahb1"/>
\r
133 <hw_channel name="tile_0.dma"/>
\r
134 <rxbuf name="tile_0.ddm"/>
\r
135 <configuration name="delay" value="0"/>
\r
136 <configuration name="cycles" value="8"/>
\r