dol/examples/arch/rdt8.xml

   1 <?xml version="1.0" encoding="UTF-8"?>\r
   2 <architecture xmlns="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE"\r
   3   xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"\r
   4   xsi:schemaLocation="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE\r
   5                       http://www.tik.ee.ethz.ch/~shapes/schema/architecture.xsd"\r
   6   name="RDT8">\r
   7   <!-- 8 Tiles communicating via a mesh of DNPs -->\r
   8 \r
   9   <!--*****************************************************************-->\r
  10   <!-- tile_0 -->\r
  11   <!--*****************************************************************-->\r
  12   <processor name="tile_0.arm" type="RISC">\r
  13   </processor>\r
  14 \r
  15   <memory name="tile_0.rdm" type="RAM">\r
  16   </memory>\r
  17 \r
  18   <hw_channel name="tile_0.armbus" type="BUS">\r
  19     <configuration name="frequency" value="100000000"/>\r
  20     <configuration name="bytespercycle" value="1"/>\r
  21   </hw_channel>\r
  22 \r
  23   <processor name="tile_0.magic" type="DSP">\r
  24   </processor>\r
  25 \r
  26   <memory name="tile_0.ddm" type="RAM">\r
  27   </memory>\r
  28 \r
  29   <hw_channel name="tile_0.magicbus" type="BUS">\r
  30     <configuration name="frequency" value="100000000"/>\r
  31     <configuration name="bytespercycle" value="1"/>\r
  32   </hw_channel>\r
  33 \r
  34   <hw_channel name="tile_0.dma" type="DMA">\r
  35     <configuration name="frequency" value="100000000"/>\r
  36     <configuration name="bytespercycle" value="1"/>\r
  37   </hw_channel>\r
  38 \r
  39   <memory name="tile_0.dxm" type="DXM">\r
  40   </memory>\r
  41 \r
  42   <hw_channel name="tile_0.ahb0" type="BUS">\r
  43     <configuration name="frequency" value="100000000"/>\r
  44     <configuration name="bytespercycle" value="1"/>\r
  45   </hw_channel>\r
  46 \r
  47   <hw_channel name="tile_0.ahb1" type="BUS">\r
  48     <configuration name="frequency" value="100000000"/>\r
  49     <configuration name="bytespercycle" value="1"/>\r
  50   </hw_channel>\r
  51 \r
  52   <hw_channel name="tile_0.dnp" type="SPI">\r
  53     <configuration name="frequency" value="100000000"/>\r
  54     <configuration name="bytespercycle" value="1"/>\r
  55   </hw_channel>\r
  56 \r
  57   <!--*****************************************************************-->\r
  58   <!-- tile_1 -->\r
  59   <!--*****************************************************************-->\r
  60   <processor name="tile_1.arm" type="RISC">\r
  61   </processor>\r
  62 \r
  63   <memory name="tile_1.rdm" type="RAM">\r
  64   </memory>\r
  65 \r
  66   <hw_channel name="tile_1.armbus" type="BUS">\r
  67    <configuration name="frequency" value="100000000"/>\r
  68    <configuration name="bytespercycle" value="1"/>\r
  69   </hw_channel>\r
  70 \r
  71   <processor name="tile_1.magic" type="DSP">\r
  72   </processor>\r
  73 \r
  74   <memory name="tile_1.ddm" type="RAM">\r
  75   </memory>\r
  76 \r
  77   <hw_channel name="tile_1.magicbus" type="BUS">\r
  78     <configuration name="frequency" value="100000000"/>\r
  79     <configuration name="bytespercycle" value="1"/>\r
  80   </hw_channel>\r
  81 \r
  82   <hw_channel name="tile_1.dma" type="DMA">\r
  83     <configuration name="frequency" value="100000000"/>\r
  84     <configuration name="bytespercycle" value="1"/>\r
  85   </hw_channel>\r
  86 \r
  87   <memory name="tile_1.dxm" type="DXM">\r
  88   </memory>\r
  89 \r
  90   <hw_channel name="tile_1.ahb0" type="BUS">\r
  91     <configuration name="frequency" value="100000000"/>\r
  92     <configuration name="bytespercycle" value="1"/>\r
  93   </hw_channel>\r
  94 \r
  95   <hw_channel name="tile_1.ahb1" type="BUS">\r
  96     <configuration name="frequency" value="100000000"/>\r
  97     <configuration name="bytespercycle" value="1"/>\r
  98   </hw_channel>\r
  99 \r
 100   <hw_channel name="tile_1.dnp" type="SPI">\r
 101     <configuration name="frequency" value="100000000"/>\r
 102     <configuration name="bytespercycle" value="1"/>\r
 103   </hw_channel>\r
 104 \r
 105   <!--*****************************************************************-->\r
 106   <!-- tile_2 -->\r
 107   <!--*****************************************************************-->\r
 108   <processor name="tile_2.arm" type="RISC">\r
 109   </processor>\r
 110 \r
 111   <memory name="tile_2.rdm" type="RAM">\r
 112   </memory>\r
 113 \r
 114   <hw_channel name="tile_2.armbus" type="BUS">\r
 115    <configuration name="frequency" value="100000000"/>\r
 116    <configuration name="bytespercycle" value="1"/>\r
 117   </hw_channel>\r
 118 \r
 119   <processor name="tile_2.magic" type="DSP">\r
 120   </processor>\r
 121 \r
 122   <memory name="tile_2.ddm" type="RAM">\r
 123   </memory>\r
 124 \r
 125   <hw_channel name="tile_2.magicbus" type="BUS">\r
 126    <configuration name="frequency" value="100000000"/>\r
 127    <configuration name="bytespercycle" value="1"/>\r
 128   </hw_channel>\r
 129 \r
 130   <hw_channel name="tile_2.dma" type="DMA">\r
 131     <configuration name="frequency" value="100000000"/>\r
 132     <configuration name="bytespercycle" value="1"/>\r
 133   </hw_channel>\r
 134 \r
 135   <memory name="tile_2.dxm" type="DXM">\r
 136   </memory>\r
 137 \r
 138   <hw_channel name="tile_2.ahb0" type="BUS">\r
 139     <configuration name="frequency" value="100000000"/>\r
 140     <configuration name="bytespercycle" value="1"/>\r
 141   </hw_channel>\r
 142 \r
 143   <hw_channel name="tile_2.ahb1" type="BUS">\r
 144    <configuration name="frequency" value="100000000"/>\r
 145    <configuration name="bytespercycle" value="1"/>\r
 146   </hw_channel>\r
 147 \r
 148   <hw_channel name="tile_2.dnp" type="SPI">\r
 149    <configuration name="frequency" value="100000000"/>\r
 150    <configuration name="bytespercycle" value="1"/>\r
 151   </hw_channel>\r
 152 \r
 153   <!--*****************************************************************-->\r
 154   <!-- tile_3 -->\r
 155   <!--*****************************************************************-->\r
 156   <processor name="tile_3.arm" type="RISC">\r
 157   </processor>\r
 158 \r
 159   <memory name="tile_3.rdm" type="RAM">\r
 160   </memory>\r
 161 \r
 162   <hw_channel name="tile_3.armbus" type="BUS">\r
 163     <configuration name="frequency" value="100000000"/>\r
 164     <configuration name="bytespercycle" value="1"/>\r
 165   </hw_channel>\r
 166 \r
 167   <processor name="tile_3.magic" type="DSP">\r
 168   </processor>\r
 169 \r
 170   <memory name="tile_3.ddm" type="RAM">\r
 171   </memory>\r
 172 \r
 173   <hw_channel name="tile_3.magicbus" type="BUS">\r
 174     <configuration name="frequency" value="100000000"/>\r
 175     <configuration name="bytespercycle" value="1"/>\r
 176   </hw_channel>\r
 177 \r
 178   <hw_channel name="tile_3.dma" type="DMA">\r
 179     <configuration name="frequency" value="100000000"/>\r
 180     <configuration name="bytespercycle" value="1"/>\r
 181   </hw_channel>\r
 182 \r
 183   <memory name="tile_3.dxm" type="DXM">\r
 184   </memory>\r
 185 \r
 186   <hw_channel name="tile_3.ahb0" type="BUS">\r
 187     <configuration name="frequency" value="100000000"/>\r
 188     <configuration name="bytespercycle" value="1"/>\r
 189   </hw_channel>\r
 190 \r
 191   <hw_channel name="tile_3.ahb1" type="BUS">\r
 192     <configuration name="frequency" value="100000000"/>\r
 193     <configuration name="bytespercycle" value="1"/>\r
 194   </hw_channel>\r
 195 \r
 196   <hw_channel name="tile_3.dnp" type="SPI">\r
 197     <configuration name="frequency" value="100000000"/>\r
 198     <configuration name="bytespercycle" value="1"/>\r
 199   </hw_channel>\r
 200 \r
 201   <!--*****************************************************************-->\r
 202   <!-- tile_4 -->\r
 203   <!--*****************************************************************-->\r
 204   <processor name="tile_4.arm" type="RISC">\r
 205   </processor>\r
 206 \r
 207   <memory name="tile_4.rdm" type="RAM">\r
 208   </memory>\r
 209 \r
 210   <hw_channel name="tile_4.armbus" type="BUS">\r
 211     <configuration name="frequency" value="100000000"/>\r
 212     <configuration name="bytespercycle" value="1"/>\r
 213   </hw_channel>\r
 214 \r
 215   <processor name="tile_4.magic" type="DSP">\r
 216   </processor>\r
 217 \r
 218   <memory name="tile_4.ddm" type="RAM">\r
 219   </memory>\r
 220 \r
 221   <hw_channel name="tile_4.magicbus" type="BUS">\r
 222     <configuration name="frequency" value="100000000"/>\r
 223     <configuration name="bytespercycle" value="1"/>\r
 224   </hw_channel>\r
 225 \r
 226   <hw_channel name="tile_4.dma" type="DMA">\r
 227     <configuration name="frequency" value="100000000"/>\r
 228     <configuration name="bytespercycle" value="1"/>\r
 229   </hw_channel>\r
 230 \r
 231   <memory name="tile_4.dxm" type="DXM">\r
 232   </memory>\r
 233 \r
 234   <hw_channel name="tile_4.ahb0" type="BUS">\r
 235     <configuration name="frequency" value="100000000"/>\r
 236     <configuration name="bytespercycle" value="1"/>\r
 237   </hw_channel>\r
 238 \r
 239   <hw_channel name="tile_4.ahb1" type="BUS">\r
 240     <configuration name="frequency" value="100000000"/>\r
 241     <configuration name="bytespercycle" value="1"/>\r
 242   </hw_channel>\r
 243 \r
 244   <hw_channel name="tile_4.dnp" type="SPI">\r
 245     <configuration name="frequency" value="100000000"/>\r
 246     <configuration name="bytespercycle" value="1"/>\r
 247   </hw_channel>\r
 248 \r
 249 \r
 250   <!--*****************************************************************-->\r
 251   <!-- tile_5 -->\r
 252   <!--*****************************************************************-->\r
 253   <processor name="tile_5.arm" type="RISC">\r
 254   </processor>\r
 255 \r
 256   <memory name="tile_5.rdm" type="RAM">\r
 257   </memory>\r
 258 \r
 259   <hw_channel name="tile_5.armbus" type="BUS">\r
 260     <configuration name="frequency" value="100000000"/>\r
 261     <configuration name="bytespercycle" value="1"/>\r
 262   </hw_channel>\r
 263 \r
 264   <processor name="tile_5.magic" type="DSP">\r
 265   </processor>\r
 266 \r
 267   <memory name="tile_5.ddm" type="RAM">\r
 268   </memory>\r
 269 \r
 270   <hw_channel name="tile_5.magicbus" type="BUS">\r
 271     <configuration name="frequency" value="100000000"/>\r
 272     <configuration name="bytespercycle" value="1"/>\r
 273   </hw_channel>\r
 274 \r
 275   <hw_channel name="tile_5.dma" type="DMA">\r
 276     <configuration name="frequency" value="100000000"/>\r
 277     <configuration name="bytespercycle" value="1"/>\r
 278   </hw_channel>\r
 279 \r
 280   <memory name="tile_5.dxm" type="DXM">\r
 281   </memory>\r
 282 \r
 283   <hw_channel name="tile_5.ahb0" type="BUS">\r
 284     <configuration name="frequency" value="100000000"/>\r
 285     <configuration name="bytespercycle" value="1"/>\r
 286   </hw_channel>\r
 287 \r
 288   <hw_channel name="tile_5.ahb1" type="BUS">\r
 289     <configuration name="frequency" value="100000000"/>\r
 290     <configuration name="bytespercycle" value="1"/>\r
 291   </hw_channel>\r
 292 \r
 293   <hw_channel name="tile_5.dnp" type="SPI">\r
 294     <configuration name="frequency" value="100000000"/>\r
 295     <configuration name="bytespercycle" value="1"/>\r
 296   </hw_channel>\r
 297 \r
 298   <!--*****************************************************************-->\r
 299   <!-- tile_6 -->\r
 300   <!--*****************************************************************-->\r
 301   <processor name="tile_6.arm" type="RISC">\r
 302   </processor>\r
 303 \r
 304   <memory name="tile_6.rdm" type="RAM">\r
 305   </memory>\r
 306 \r
 307   <hw_channel name="tile_6.armbus" type="BUS">\r
 308     <configuration name="frequency" value="100000000"/>\r
 309     <configuration name="bytespercycle" value="1"/>\r
 310   </hw_channel>\r
 311 \r
 312   <processor name="tile_6.magic" type="DSP">\r
 313   </processor>\r
 314 \r
 315   <memory name="tile_6.ddm" type="RAM">\r
 316   </memory>\r
 317 \r
 318   <hw_channel name="tile_6.magicbus" type="BUS">\r
 319     <configuration name="frequency" value="100000000"/>\r
 320     <configuration name="bytespercycle" value="1"/>\r
 321   </hw_channel>\r
 322 \r
 323   <hw_channel name="tile_6.dma" type="DMA">\r
 324     <configuration name="frequency" value="100000000"/>\r
 325     <configuration name="bytespercycle" value="1"/>\r
 326   </hw_channel>\r
 327 \r
 328   <memory name="tile_6.dxm" type="DXM">\r
 329   </memory>\r
 330 \r
 331   <hw_channel name="tile_6.ahb0" type="BUS">\r
 332     <configuration name="frequency" value="100000000"/>\r
 333     <configuration name="bytespercycle" value="1"/>\r
 334   </hw_channel>\r
 335 \r
 336   <hw_channel name="tile_6.ahb1" type="BUS">\r
 337     <configuration name="frequency" value="100000000"/>\r
 338     <configuration name="bytespercycle" value="1"/>\r
 339   </hw_channel>\r
 340 \r
 341   <hw_channel name="tile_6.dnp" type="SPI">\r
 342     <configuration name="frequency" value="100000000"/>\r
 343     <configuration name="bytespercycle" value="1"/>\r
 344   </hw_channel>\r
 345 \r
 346 \r
 347   <!--*****************************************************************-->\r
 348   <!-- tile_7 -->\r
 349   <!--*****************************************************************-->\r
 350   <processor name="tile_7.arm" type="RISC">\r
 351   </processor>\r
 352 \r
 353   <memory name="tile_7.rdm" type="RAM">\r
 354   </memory>\r
 355 \r
 356   <hw_channel name="tile_7.armbus" type="BUS">\r
 357     <configuration name="frequency" value="100000000"/>\r
 358     <configuration name="bytespercycle" value="1"/>\r
 359   </hw_channel>\r
 360 \r
 361   <processor name="tile_7.magic" type="DSP">\r
 362   </processor>\r
 363 \r
 364   <memory name="tile_7.ddm" type="RAM">\r
 365   </memory>\r
 366 \r
 367   <hw_channel name="tile_7.magicbus" type="BUS">\r
 368     <configuration name="frequency" value="100000000"/>\r
 369     <configuration name="bytespercycle" value="1"/>\r
 370   </hw_channel>\r
 371 \r
 372   <hw_channel name="tile_7.dma" type="DMA">\r
 373     <configuration name="frequency" value="100000000"/>\r
 374     <configuration name="bytespercycle" value="1"/>\r
 375   </hw_channel>\r
 376 \r
 377   <memory name="tile_7.dxm" type="DXM">\r
 378   </memory>\r
 379 \r
 380   <hw_channel name="tile_7.ahb0" type="BUS">\r
 381     <configuration name="frequency" value="100000000"/>\r
 382     <configuration name="bytespercycle" value="1"/>\r
 383   </hw_channel>\r
 384 \r
 385   <hw_channel name="tile_7.ahb1" type="BUS">\r
 386     <configuration name="frequency" value="100000000"/>\r
 387     <configuration name="bytespercycle" value="1"/>\r
 388   </hw_channel>\r
 389 \r
 390   <hw_channel name="tile_7.dnp" type="SPI">\r
 391     <configuration name="frequency" value="100000000"/>\r
 392     <configuration name="bytespercycle" value="1"/>\r
 393   </hw_channel>\r
 394 \r
 395 \r
 396   <!--*****************************************************************-->\r
 397   <!-- tile_0 communication paths -->\r
 398   <!--*****************************************************************-->\r
 399   <writepath name="tile_0.rdmtodxm">\r
 400     <processor name="tile_0.arm"/>\r
 401     <txbuf name="tile_0.rdm"/>\r
 402     <hw_channel name="tile_0.armbus"/>\r
 403     <hw_channel name="tile_0.ahb1"/>\r
 404     <chbuf name="tile_0.dxm"/>\r
 405     <configuration name="delay" value="0"/>\r
 406     <configuration name="cycles" value="8"/>\r
 407   </writepath>\r
 408 \r
 409   <readpath name="tile_0.rdmfromdxm">\r
 410     <processor name="tile_0.arm"/>\r
 411     <chbuf name="tile_0.dxm"/>\r
 412     <hw_channel name="tile_0.ahb1"/>\r
 413     <hw_channel name="tile_0.armbus"/>\r
 414     <rxbuf name="tile_0.rdm"/>\r
 415     <configuration name="delay" value="0"/>\r
 416     <configuration name="cycles" value="8"/>\r
 417   </readpath>\r
 418 \r
 419   <writepath name="tile_0.rdmtordm">\r
 420     <processor name="tile_0.arm"/>\r
 421     <txbuf name="tile_0.rdm"/>\r
 422     <hw_channel name="tile_0.armbus"/>\r
 423     <chbuf name="tile_0.rdm"/>\r
 424     <configuration name="delay" value="0"/>\r
 425     <configuration name="cycles" value="8"/>\r
 426   </writepath>\r
 427 \r
 428   <readpath name="tile_0.rdmfromrdm">\r
 429     <processor name="tile_0.arm"/>\r
 430     <chbuf name="tile_0.rdm"/>\r
 431     <hw_channel name="tile_0.armbus"/>\r
 432     <rxbuf name="tile_0.rdm"/>\r
 433     <configuration name="delay" value="0"/>\r
 434     <configuration name="cycles" value="8"/>\r
 435   </readpath>\r
 436 \r
 437   <writepath name="tile_0.ddmtoddm">\r
 438     <processor name="tile_0.magic"/>\r
 439     <txbuf name="tile_0.ddm"/>\r
 440     <hw_channel name="tile_0.magicbus"/>\r
 441     <chbuf name="tile_0.ddm"/>\r
 442     <configuration name="delay" value="0"/>\r
 443     <configuration name="cycles" value="8"/>\r
 444   </writepath>\r
 445 \r
 446   <readpath name="tile_0.ddmfromddm">\r
 447     <processor name="tile_0.magic"/>\r
 448     <chbuf name="tile_0.ddm"/>\r
 449     <hw_channel name="tile_0.magicbus"/>\r
 450     <rxbuf name="tile_0.ddm"/>\r
 451     <configuration name="delay" value="0"/>\r
 452     <configuration name="cycles" value="8"/>\r
 453   </readpath>\r
 454 \r
 455   <writepath name="tile_0.ddmtodxm">\r
 456     <processor name="tile_0.magic"/>\r
 457     <txbuf name="tile_0.ddm"/>\r
 458     <hw_channel name="tile_0.dma"/>\r
 459     <hw_channel name="tile_0.ahb1"/>\r
 460     <chbuf name="tile_0.dxm"/>\r
 461     <configuration name="delay" value="0"/>\r
 462     <configuration name="cycles" value="8"/>\r
 463   </writepath>\r
 464 \r
 465   <readpath name="tile_0.ddmfromdxm">\r
 466     <processor name="tile_0.magic"/>\r
 467     <chbuf name="tile_0.dxm"/>\r
 468     <hw_channel name="tile_0.ahb1"/>\r
 469     <hw_channel name="tile_0.dma"/>\r
 470     <rxbuf name="tile_0.ddm"/>\r
 471     <configuration name="delay" value="0"/>\r
 472     <configuration name="cycles" value="8"/>\r
 473   </readpath>\r
 474 \r
 475   <!-- tile_0 ARM inter-tile communication paths -->\r
 476   <writepath name="tile_0.rdmtodnp_1">\r
 477     <processor name="tile_0.arm"/>\r
 478     <txbuf name="tile_0.rdm"/>\r
 479     <hw_channel name="tile_0.ahb0"/>\r
 480     <hw_channel name="tile_0.dnp"/>\r
 481     <hw_channel name="tile_1.dnp"/>\r
 482     <chbuf name="tile_1.dxm"/>\r
 483   </writepath>\r
 484 \r
 485   <writepath name="tile_0.rdmtodnp_2">\r
 486     <processor name="tile_0.arm"/>\r
 487     <txbuf name="tile_0.rdm"/>\r
 488     <hw_channel name="tile_0.ahb0"/>\r
 489     <hw_channel name="tile_0.dnp"/>\r
 490     <hw_channel name="tile_2.dnp"/>\r
 491     <chbuf name="tile_2.dxm"/>\r
 492   </writepath>\r
 493 \r
 494   <writepath name="tile_0.rdmtodnp_3">\r
 495     <processor name="tile_0.arm"/>\r
 496     <txbuf name="tile_0.rdm"/>\r
 497     <hw_channel name="tile_0.ahb0"/>\r
 498     <hw_channel name="tile_0.dnp"/>\r
 499     <hw_channel name="tile_3.dnp"/>\r
 500     <chbuf name="tile_3.dxm"/>\r
 501   </writepath>\r
 502 \r
 503   <writepath name="tile_0.rdmtodnp_4">\r
 504     <processor name="tile_0.arm"/>\r
 505     <txbuf name="tile_0.rdm"/>\r
 506     <hw_channel name="tile_0.ahb0"/>\r
 507     <hw_channel name="tile_0.dnp"/>\r
 508     <hw_channel name="tile_4.dnp"/>\r
 509     <chbuf name="tile_4.dxm"/>\r
 510   </writepath>\r
 511 \r
 512   <writepath name="tile_0.rdmtodnp_5">\r
 513     <processor name="tile_0.arm"/>\r
 514     <txbuf name="tile_0.rdm"/>\r
 515     <hw_channel name="tile_0.ahb0"/>\r
 516     <hw_channel name="tile_0.dnp"/>\r
 517     <hw_channel name="tile_5.dnp"/>\r
 518     <chbuf name="tile_5.dxm"/>\r
 519   </writepath>\r
 520 \r
 521   <writepath name="tile_0.rdmtodnp_6">\r
 522     <processor name="tile_0.arm"/>\r
 523     <txbuf name="tile_0.rdm"/>\r
 524     <hw_channel name="tile_0.ahb0"/>\r
 525     <hw_channel name="tile_0.dnp"/>\r
 526     <hw_channel name="tile_6.dnp"/>\r
 527     <chbuf name="tile_6.dxm"/>\r
 528   </writepath>\r
 529 \r
 530   <writepath name="tile_0.rdmtodnp_7">\r
 531     <processor name="tile_0.arm"/>\r
 532     <txbuf name="tile_0.rdm"/>\r
 533     <hw_channel name="tile_0.ahb0"/>\r
 534     <hw_channel name="tile_0.dnp"/>\r
 535     <hw_channel name="tile_7.dnp"/>\r
 536     <chbuf name="tile_7.dxm"/>\r
 537   </writepath>\r
 538 \r
 539   <!-- tile_0 DSP inter-tile communication paths -->\r
 540   <writepath name="tile_0.ddmtodnp_1">\r
 541     <processor name="tile_0.magic"/>\r
 542     <txbuf name="tile_0.ddm"/>\r
 543     <hw_channel name="tile_0.ahb0"/>\r
 544     <hw_channel name="tile_0.dnp"/>\r
 545     <hw_channel name="tile_1.dnp"/>\r
 546     <chbuf name="tile_1.dxm"/>\r
 547   </writepath>\r
 548 \r
 549   <writepath name="tile_0.ddmtodnp_2">\r
 550     <processor name="tile_0.magic"/>\r
 551     <txbuf name="tile_0.ddm"/>\r
 552     <hw_channel name="tile_0.ahb0"/>\r
 553     <hw_channel name="tile_0.dnp"/>\r
 554     <hw_channel name="tile_2.dnp"/>\r
 555     <chbuf name="tile_2.dxm"/>\r
 556   </writepath>\r
 557 \r
 558   <writepath name="tile_0.ddmtodnp_3">\r
 559     <processor name="tile_0.magic"/>\r
 560     <txbuf name="tile_0.ddm"/>\r
 561     <hw_channel name="tile_0.ahb0"/>\r
 562     <hw_channel name="tile_0.dnp"/>\r
 563     <hw_channel name="tile_3.dnp"/>\r
 564     <chbuf name="tile_3.dxm"/>\r
 565   </writepath>\r
 566 \r
 567   <writepath name="tile_0.ddmtodnp_4">\r
 568     <processor name="tile_0.magic"/>\r
 569     <txbuf name="tile_0.ddm"/>\r
 570     <hw_channel name="tile_0.ahb0"/>\r
 571     <hw_channel name="tile_0.dnp"/>\r
 572     <hw_channel name="tile_4.dnp"/>\r
 573     <chbuf name="tile_4.dxm"/>\r
 574   </writepath>\r
 575 \r
 576   <writepath name="tile_0.ddmtodnp_5">\r
 577     <processor name="tile_0.magic"/>\r
 578     <txbuf name="tile_0.ddm"/>\r
 579     <hw_channel name="tile_0.ahb0"/>\r
 580     <hw_channel name="tile_0.dnp"/>\r
 581     <hw_channel name="tile_5.dnp"/>\r
 582     <chbuf name="tile_5.dxm"/>\r
 583   </writepath>\r
 584 \r
 585   <writepath name="tile_0.ddmtodnp_6">\r
 586     <processor name="tile_0.magic"/>\r
 587     <txbuf name="tile_0.ddm"/>\r
 588     <hw_channel name="tile_0.ahb0"/>\r
 589     <hw_channel name="tile_0.dnp"/>\r
 590     <hw_channel name="tile_6.dnp"/>\r
 591     <chbuf name="tile_6.dxm"/>\r
 592   </writepath>\r
 593 \r
 594   <writepath name="tile_0.ddmtodnp_7">\r
 595     <processor name="tile_0.magic"/>\r
 596     <txbuf name="tile_0.ddm"/>\r
 597     <hw_channel name="tile_0.ahb0"/>\r
 598     <hw_channel name="tile_0.dnp"/>\r
 599     <hw_channel name="tile_7.dnp"/>\r
 600     <chbuf name="tile_7.dxm"/>\r
 601   </writepath>\r
 602 \r
 603 \r
 604   <!--*****************************************************************-->\r
 605   <!-- tile_1 communication paths -->\r
 606   <!--*****************************************************************-->\r
 607   <writepath name="tile_1.rdmtodxm">\r
 608     <processor name="tile_1.arm"/>\r
 609     <txbuf name="tile_1.rdm"/>\r
 610     <hw_channel name="tile_1.armbus"/>\r
 611     <hw_channel name="tile_1.ahb1"/>\r
 612     <chbuf name="tile_1.dxm"/>\r
 613     <configuration name="delay" value="0"/>\r
 614     <configuration name="cycles" value="8"/>\r
 615   </writepath>\r
 616 \r
 617   <readpath name="tile_1.rdmfromdxm">\r
 618     <processor name="tile_1.arm"/>\r
 619     <chbuf name="tile_1.dxm"/>\r
 620     <hw_channel name="tile_1.ahb1"/>\r
 621     <hw_channel name="tile_1.armbus"/>\r
 622     <rxbuf name="tile_1.rdm"/>\r
 623     <configuration name="delay" value="0"/>\r
 624     <configuration name="cycles" value="8"/>\r
 625   </readpath>\r
 626 \r
 627   <writepath name="tile_1.rdmtordm">\r
 628     <processor name="tile_1.arm"/>\r
 629     <txbuf name="tile_1.rdm"/>\r
 630     <hw_channel name="tile_1.armbus"/>\r
 631     <chbuf name="tile_1.rdm"/>\r
 632     <configuration name="delay" value="0"/>\r
 633     <configuration name="cycles" value="8"/>\r
 634   </writepath>\r
 635 \r
 636   <readpath name="tile_1.rdmfromrdm">\r
 637     <processor name="tile_1.arm"/>\r
 638     <chbuf name="tile_1.rdm"/>\r
 639     <hw_channel name="tile_1.armbus"/>\r
 640     <rxbuf name="tile_1.rdm"/>\r
 641     <configuration name="delay" value="0"/>\r
 642     <configuration name="cycles" value="8"/>\r
 643   </readpath>\r
 644 \r
 645   <writepath name="tile_1.ddmtoddm">\r
 646     <processor name="tile_1.magic"/>\r
 647     <txbuf name="tile_1.ddm"/>\r
 648     <hw_channel name="tile_1.magicbus"/>\r
 649     <chbuf name="tile_1.ddm"/>\r
 650     <configuration name="delay" value="0"/>\r
 651     <configuration name="cycles" value="8"/>\r
 652   </writepath>\r
 653 \r
 654   <readpath name="tile_1.ddmfromddm">\r
 655     <processor name="tile_1.magic"/>\r
 656     <chbuf name="tile_1.ddm"/>\r
 657     <hw_channel name="tile_1.magicbus"/>\r
 658     <rxbuf name="tile_1.ddm"/>\r
 659     <configuration name="delay" value="0"/>\r
 660     <configuration name="cycles" value="8"/>\r
 661   </readpath>\r
 662 \r
 663   <writepath name="tile_1.ddmtodxm">\r
 664     <processor name="tile_1.magic"/>\r
 665     <txbuf name="tile_1.ddm"/>\r
 666     <hw_channel name="tile_1.dma"/>\r
 667     <hw_channel name="tile_1.ahb1"/>\r
 668     <chbuf name="tile_1.dxm"/>\r
 669     <configuration name="delay" value="0"/>\r
 670     <configuration name="cycles" value="8"/>\r
 671   </writepath>\r
 672 \r
 673   <readpath name="tile_1.ddmfromdxm">\r
 674     <processor name="tile_1.magic"/>\r
 675     <chbuf name="tile_1.dxm"/>\r
 676     <hw_channel name="tile_1.ahb1"/>\r
 677     <hw_channel name="tile_1.dma"/>\r
 678     <rxbuf name="tile_1.ddm"/>\r
 679     <configuration name="delay" value="0"/>\r
 680     <configuration name="cycles" value="8"/>\r
 681   </readpath>\r
 682 \r
 683   <!-- tile_1 ARM inter-tile communication paths -->\r
 684   <writepath name="tile_1.rdmtodnp_0">\r
 685     <processor name="tile_1.arm"/>\r
 686     <txbuf name="tile_1.rdm"/>\r
 687     <hw_channel name="tile_1.ahb0"/>\r
 688     <hw_channel name="tile_1.dnp"/>\r
 689     <hw_channel name="tile_0.dnp"/>\r
 690     <chbuf name="tile_0.dxm"/>\r
 691   </writepath>\r
 692 \r
 693   <writepath name="tile_1.rdmtodnp_2">\r
 694     <processor name="tile_1.arm"/>\r
 695     <txbuf name="tile_1.rdm"/>\r
 696     <hw_channel name="tile_1.ahb0"/>\r
 697     <hw_channel name="tile_1.dnp"/>\r
 698     <hw_channel name="tile_2.dnp"/>\r
 699     <chbuf name="tile_2.dxm"/>\r
 700   </writepath>\r
 701 \r
 702   <writepath name="tile_1.rdmtodnp_3">\r
 703     <processor name="tile_1.arm"/>\r
 704     <txbuf name="tile_1.rdm"/>\r
 705     <hw_channel name="tile_1.ahb0"/>\r
 706     <hw_channel name="tile_1.dnp"/>\r
 707     <hw_channel name="tile_3.dnp"/>\r
 708     <chbuf name="tile_3.dxm"/>\r
 709   </writepath>\r
 710 \r
 711   <writepath name="tile_1.rdmtodnp_4">\r
 712     <processor name="tile_1.arm"/>\r
 713     <txbuf name="tile_1.rdm"/>\r
 714     <hw_channel name="tile_1.ahb0"/>\r
 715     <hw_channel name="tile_1.dnp"/>\r
 716     <hw_channel name="tile_4.dnp"/>\r
 717     <chbuf name="tile_4.dxm"/>\r
 718   </writepath>\r
 719 \r
 720   <writepath name="tile_1.rdmtodnp_5">\r
 721     <processor name="tile_1.arm"/>\r
 722     <txbuf name="tile_1.rdm"/>\r
 723     <hw_channel name="tile_1.ahb0"/>\r
 724     <hw_channel name="tile_1.dnp"/>\r
 725     <hw_channel name="tile_5.dnp"/>\r
 726     <chbuf name="tile_5.dxm"/>\r
 727   </writepath>\r
 728 \r
 729   <writepath name="tile_1.rdmtodnp_6">\r
 730     <processor name="tile_1.arm"/>\r
 731     <txbuf name="tile_1.rdm"/>\r
 732     <hw_channel name="tile_1.ahb0"/>\r
 733     <hw_channel name="tile_1.dnp"/>\r
 734     <hw_channel name="tile_6.dnp"/>\r
 735     <chbuf name="tile_6.dxm"/>\r
 736   </writepath>\r
 737 \r
 738   <writepath name="tile_1.rdmtodnp_7">\r
 739     <processor name="tile_1.arm"/>\r
 740     <txbuf name="tile_1.rdm"/>\r
 741     <hw_channel name="tile_1.ahb0"/>\r
 742     <hw_channel name="tile_1.dnp"/>\r
 743     <hw_channel name="tile_7.dnp"/>\r
 744     <chbuf name="tile_7.dxm"/>\r
 745   </writepath>\r
 746 \r
 747   <!-- tile_1 DSP inter-tile communication paths -->\r
 748   <writepath name="tile_1.ddmtodnp_0">\r
 749     <processor name="tile_1.magic"/>\r
 750     <txbuf name="tile_1.ddm"/>\r
 751     <hw_channel name="tile_1.ahb0"/>\r
 752     <hw_channel name="tile_1.dnp"/>\r
 753     <hw_channel name="tile_0.dnp"/>\r
 754     <chbuf name="tile_0.dxm"/>\r
 755   </writepath>\r
 756 \r
 757   <writepath name="tile_1.ddmtodnp_2">\r
 758     <processor name="tile_1.magic"/>\r
 759     <txbuf name="tile_1.ddm"/>\r
 760     <hw_channel name="tile_1.ahb0"/>\r
 761     <hw_channel name="tile_1.dnp"/>\r
 762     <hw_channel name="tile_2.dnp"/>\r
 763     <chbuf name="tile_2.dxm"/>\r
 764   </writepath>\r
 765 \r
 766   <writepath name="tile_1.ddmtodnp_3">\r
 767     <processor name="tile_1.magic"/>\r
 768     <txbuf name="tile_1.ddm"/>\r
 769     <hw_channel name="tile_1.ahb0"/>\r
 770     <hw_channel name="tile_1.dnp"/>\r
 771     <hw_channel name="tile_3.dnp"/>\r
 772     <chbuf name="tile_3.dxm"/>\r
 773   </writepath>\r
 774 \r
 775   <writepath name="tile_1.ddmtodnp_4">\r
 776     <processor name="tile_1.magic"/>\r
 777     <txbuf name="tile_1.ddm"/>\r
 778     <hw_channel name="tile_1.ahb0"/>\r
 779     <hw_channel name="tile_1.dnp"/>\r
 780     <hw_channel name="tile_4.dnp"/>\r
 781     <chbuf name="tile_4.dxm"/>\r
 782   </writepath>\r
 783 \r
 784   <writepath name="tile_1.ddmtodnp_5">\r
 785     <processor name="tile_1.magic"/>\r
 786     <txbuf name="tile_1.ddm"/>\r
 787     <hw_channel name="tile_1.ahb0"/>\r
 788     <hw_channel name="tile_1.dnp"/>\r
 789     <hw_channel name="tile_5.dnp"/>\r
 790     <chbuf name="tile_5.dxm"/>\r
 791   </writepath>\r
 792 \r
 793   <writepath name="tile_1.ddmtodnp_6">\r
 794     <processor name="tile_1.magic"/>\r
 795     <txbuf name="tile_1.ddm"/>\r
 796     <hw_channel name="tile_1.ahb0"/>\r
 797     <hw_channel name="tile_1.dnp"/>\r
 798     <hw_channel name="tile_6.dnp"/>\r
 799     <chbuf name="tile_6.dxm"/>\r
 800   </writepath>\r
 801 \r
 802   <writepath name="tile_1.ddmtodnp_7">\r
 803     <processor name="tile_1.magic"/>\r
 804     <txbuf name="tile_1.ddm"/>\r
 805     <hw_channel name="tile_1.ahb0"/>\r
 806     <hw_channel name="tile_1.dnp"/>\r
 807     <hw_channel name="tile_7.dnp"/>\r
 808     <chbuf name="tile_7.dxm"/>\r
 809   </writepath>\r
 810 \r
 811 \r
 812   <!--*****************************************************************-->\r
 813   <!-- tile_2 communication paths -->\r
 814   <!--*****************************************************************-->\r
 815   <writepath name="tile_2.rdmtodxm">\r
 816     <processor name="tile_2.arm"/>\r
 817     <txbuf name="tile_2.rdm"/>\r
 818     <hw_channel name="tile_2.armbus"/>\r
 819     <hw_channel name="tile_2.ahb1"/>\r
 820     <chbuf name="tile_2.dxm"/>\r
 821     <configuration name="delay" value="0"/>\r
 822     <configuration name="cycles" value="8"/>\r
 823   </writepath>\r
 824 \r
 825   <readpath name="tile_2.rdmfromdxm">\r
 826     <processor name="tile_2.arm"/>\r
 827     <chbuf name="tile_2.dxm"/>\r
 828     <hw_channel name="tile_2.ahb1"/>\r
 829     <hw_channel name="tile_2.armbus"/>\r
 830     <rxbuf name="tile_2.rdm"/>\r
 831     <configuration name="delay" value="0"/>\r
 832     <configuration name="cycles" value="8"/>\r
 833   </readpath>\r
 834 \r
 835   <writepath name="tile_2.rdmtordm">\r
 836     <processor name="tile_2.arm"/>\r
 837     <txbuf name="tile_2.rdm"/>\r
 838     <hw_channel name="tile_2.armbus"/>\r
 839     <chbuf name="tile_2.rdm"/>\r
 840     <configuration name="delay" value="0"/>\r
 841     <configuration name="cycles" value="8"/>\r
 842   </writepath>\r
 843 \r
 844   <readpath name="tile_2.rdmfromrdm">\r
 845     <processor name="tile_2.arm"/>\r
 846     <chbuf name="tile_2.rdm"/>\r
 847     <hw_channel name="tile_2.armbus"/>\r
 848     <rxbuf name="tile_2.rdm"/>\r
 849     <configuration name="delay" value="0"/>\r
 850     <configuration name="cycles" value="8"/>\r
 851   </readpath>\r
 852 \r
 853   <writepath name="tile_2.ddmtoddm">\r
 854     <processor name="tile_2.magic"/>\r
 855     <txbuf name="tile_2.ddm"/>\r
 856     <hw_channel name="tile_2.magicbus"/>\r
 857     <chbuf name="tile_2.ddm"/>\r
 858     <configuration name="delay" value="0"/>\r
 859     <configuration name="cycles" value="8"/>\r
 860   </writepath>\r
 861 \r
 862   <readpath name="tile_2.ddmfromddm">\r
 863     <processor name="tile_2.magic"/>\r
 864     <chbuf name="tile_2.ddm"/>\r
 865     <hw_channel name="tile_2.magicbus"/>\r
 866     <rxbuf name="tile_2.ddm"/>\r
 867     <configuration name="delay" value="0"/>\r
 868     <configuration name="cycles" value="8"/>\r
 869   </readpath>\r
 870 \r
 871   <writepath name="tile_2.ddmtodxm">\r
 872     <processor name="tile_2.magic"/>\r
 873     <txbuf name="tile_2.ddm"/>\r
 874     <hw_channel name="tile_2.dma"/>\r
 875     <hw_channel name="tile_2.ahb1"/>\r
 876     <chbuf name="tile_2.dxm"/>\r
 877     <configuration name="delay" value="0"/>\r
 878     <configuration name="cycles" value="8"/>\r
 879   </writepath>\r
 880 \r
 881   <readpath name="tile_2.ddmfromdxm">\r
 882     <processor name="tile_2.magic"/>\r
 883     <chbuf name="tile_2.dxm"/>\r
 884     <hw_channel name="tile_2.ahb1"/>\r
 885     <hw_channel name="tile_2.dma"/>\r
 886     <rxbuf name="tile_2.ddm"/>\r
 887     <configuration name="delay" value="0"/>\r
 888     <configuration name="cycles" value="8"/>\r
 889   </readpath>\r
 890 \r
 891   <!-- tile_2 ARM inter-tile communication paths -->\r
 892   <writepath name="tile_2.rdmtodnp_0">\r
 893     <processor name="tile_2.arm"/>\r
 894     <txbuf name="tile_2.rdm"/>\r
 895     <hw_channel name="tile_2.ahb0"/>\r
 896     <hw_channel name="tile_2.dnp"/>\r
 897     <hw_channel name="tile_0.dnp"/>\r
 898     <chbuf name="tile_0.dxm"/>\r
 899   </writepath>\r
 900 \r
 901   <writepath name="tile_2.rdmtodnp_1">\r
 902     <processor name="tile_2.arm"/>\r
 903     <txbuf name="tile_2.rdm"/>\r
 904     <hw_channel name="tile_2.ahb0"/>\r
 905     <hw_channel name="tile_2.dnp"/>\r
 906     <hw_channel name="tile_1.dnp"/>\r
 907     <chbuf name="tile_1.dxm"/>\r
 908   </writepath>\r
 909 \r
 910   <writepath name="tile_2.rdmtodnp_3">\r
 911     <processor name="tile_2.arm"/>\r
 912     <txbuf name="tile_2.rdm"/>\r
 913     <hw_channel name="tile_2.ahb0"/>\r
 914     <hw_channel name="tile_2.dnp"/>\r
 915     <hw_channel name="tile_3.dnp"/>\r
 916     <chbuf name="tile_3.dxm"/>\r
 917   </writepath>\r
 918 \r
 919   <writepath name="tile_2.rdmtodnp_4">\r
 920     <processor name="tile_2.arm"/>\r
 921     <txbuf name="tile_2.rdm"/>\r
 922     <hw_channel name="tile_2.ahb0"/>\r
 923     <hw_channel name="tile_2.dnp"/>\r
 924     <hw_channel name="tile_4.dnp"/>\r
 925     <chbuf name="tile_4.dxm"/>\r
 926   </writepath>\r
 927 \r
 928   <writepath name="tile_2.rdmtodnp_5">\r
 929     <processor name="tile_2.arm"/>\r
 930     <txbuf name="tile_2.rdm"/>\r
 931     <hw_channel name="tile_2.ahb0"/>\r
 932     <hw_channel name="tile_2.dnp"/>\r
 933     <hw_channel name="tile_5.dnp"/>\r
 934     <chbuf name="tile_5.dxm"/>\r
 935   </writepath>\r
 936 \r
 937   <writepath name="tile_2.rdmtodnp_6">\r
 938     <processor name="tile_2.arm"/>\r
 939     <txbuf name="tile_2.rdm"/>\r
 940     <hw_channel name="tile_2.ahb0"/>\r
 941     <hw_channel name="tile_2.dnp"/>\r
 942     <hw_channel name="tile_6.dnp"/>\r
 943     <chbuf name="tile_6.dxm"/>\r
 944   </writepath>\r
 945 \r
 946   <writepath name="tile_2.rdmtodnp_7">\r
 947     <processor name="tile_2.arm"/>\r
 948     <txbuf name="tile_2.rdm"/>\r
 949     <hw_channel name="tile_2.ahb0"/>\r
 950     <hw_channel name="tile_2.dnp"/>\r
 951     <hw_channel name="tile_7.dnp"/>\r
 952     <chbuf name="tile_7.dxm"/>\r
 953   </writepath>\r
 954 \r
 955   <!-- tile_2 DSP inter-tile communication paths -->\r
 956   <writepath name="tile_2.ddmtodnp_0">\r
 957     <processor name="tile_2.magic"/>\r
 958     <txbuf name="tile_2.ddm"/>\r
 959     <hw_channel name="tile_2.ahb0"/>\r
 960     <hw_channel name="tile_2.dnp"/>\r
 961     <hw_channel name="tile_0.dnp"/>\r
 962     <chbuf name="tile_0.dxm"/>\r
 963   </writepath>\r
 964 \r
 965   <writepath name="tile_2.ddmtodnp_1">\r
 966     <processor name="tile_2.magic"/>\r
 967     <txbuf name="tile_2.ddm"/>\r
 968     <hw_channel name="tile_2.ahb0"/>\r
 969     <hw_channel name="tile_2.dnp"/>\r
 970     <hw_channel name="tile_1.dnp"/>\r
 971     <chbuf name="tile_1.dxm"/>\r
 972   </writepath>\r
 973 \r
 974   <writepath name="tile_2.ddmtodnp_3">\r
 975     <processor name="tile_2.magic"/>\r
 976     <txbuf name="tile_2.ddm"/>\r
 977     <hw_channel name="tile_2.ahb0"/>\r
 978     <hw_channel name="tile_2.dnp"/>\r
 979     <hw_channel name="tile_3.dnp"/>\r
 980     <chbuf name="tile_3.dxm"/>\r
 981   </writepath>\r
 982 \r
 983   <writepath name="tile_2.ddmtodnp_4">\r
 984     <processor name="tile_2.magic"/>\r
 985     <txbuf name="tile_2.ddm"/>\r
 986     <hw_channel name="tile_2.ahb0"/>\r
 987     <hw_channel name="tile_2.dnp"/>\r
 988     <hw_channel name="tile_4.dnp"/>\r
 989     <chbuf name="tile_4.dxm"/>\r
 990   </writepath>\r
 991 \r
 992   <writepath name="tile_2.ddmtodnp_5">\r
 993     <processor name="tile_2.magic"/>\r
 994     <txbuf name="tile_2.ddm"/>\r
 995     <hw_channel name="tile_2.ahb0"/>\r
 996     <hw_channel name="tile_2.dnp"/>\r
 997     <hw_channel name="tile_5.dnp"/>\r
 998     <chbuf name="tile_5.dxm"/>\r
 999   </writepath>\r
1000 \r
1001   <writepath name="tile_2.ddmtodnp_6">\r
1002     <processor name="tile_2.magic"/>\r
1003     <txbuf name="tile_2.ddm"/>\r
1004     <hw_channel name="tile_2.ahb0"/>\r
1005     <hw_channel name="tile_2.dnp"/>\r
1006     <hw_channel name="tile_6.dnp"/>\r
1007     <chbuf name="tile_6.dxm"/>\r
1008   </writepath>\r
1009 \r
1010   <writepath name="tile_2.ddmtodnp_7">\r
1011     <processor name="tile_2.magic"/>\r
1012     <txbuf name="tile_2.ddm"/>\r
1013     <hw_channel name="tile_2.ahb0"/>\r
1014     <hw_channel name="tile_2.dnp"/>\r
1015     <hw_channel name="tile_7.dnp"/>\r
1016     <chbuf name="tile_7.dxm"/>\r
1017   </writepath>\r
1018 \r
1019 \r
1020   <!--*****************************************************************-->\r
1021   <!-- tile_3 communication paths -->\r
1022   <!--*****************************************************************-->\r
1023   <writepath name="tile_3.rdmtodxm">\r
1024     <processor name="tile_3.arm"/>\r
1025     <txbuf name="tile_3.rdm"/>\r
1026     <hw_channel name="tile_3.armbus"/>\r
1027     <hw_channel name="tile_3.ahb1"/>\r
1028     <chbuf name="tile_3.dxm"/>\r
1029     <configuration name="delay" value="0"/>\r
1030     <configuration name="cycles" value="8"/>\r
1031   </writepath>\r
1032 \r
1033   <readpath name="tile_3.rdmfromdxm">\r
1034     <processor name="tile_3.arm"/>\r
1035     <chbuf name="tile_3.dxm"/>\r
1036     <hw_channel name="tile_3.ahb1"/>\r
1037     <hw_channel name="tile_3.armbus"/>\r
1038     <rxbuf name="tile_3.rdm"/>\r
1039     <configuration name="delay" value="0"/>\r
1040     <configuration name="cycles" value="8"/>\r
1041   </readpath>\r
1042 \r
1043   <writepath name="tile_3.rdmtordm">\r
1044     <processor name="tile_3.arm"/>\r
1045     <txbuf name="tile_3.rdm"/>\r
1046     <hw_channel name="tile_3.armbus"/>\r
1047     <chbuf name="tile_3.rdm"/>\r
1048     <configuration name="delay" value="0"/>\r
1049     <configuration name="cycles" value="8"/>\r
1050   </writepath>\r
1051 \r
1052   <readpath name="tile_3.rdmfromrdm">\r
1053     <processor name="tile_3.arm"/>\r
1054     <chbuf name="tile_3.rdm"/>\r
1055     <hw_channel name="tile_3.armbus"/>\r
1056     <rxbuf name="tile_3.rdm"/>\r
1057     <configuration name="delay" value="0"/>\r
1058     <configuration name="cycles" value="8"/>\r
1059   </readpath>\r
1060 \r
1061   <writepath name="tile_3.ddmtoddm">\r
1062     <processor name="tile_3.magic"/>\r
1063     <txbuf name="tile_3.ddm"/>\r
1064     <hw_channel name="tile_3.magicbus"/>\r
1065     <chbuf name="tile_3.ddm"/>\r
1066     <configuration name="delay" value="0"/>\r
1067     <configuration name="cycles" value="8"/>\r
1068   </writepath>\r
1069 \r
1070   <readpath name="tile_3.ddmfromddm">\r
1071     <processor name="tile_3.magic"/>\r
1072     <chbuf name="tile_3.ddm"/>\r
1073     <hw_channel name="tile_3.magicbus"/>\r
1074     <rxbuf name="tile_3.ddm"/>\r
1075     <configuration name="delay" value="0"/>\r
1076     <configuration name="cycles" value="8"/>\r
1077   </readpath>\r
1078 \r
1079   <writepath name="tile_3.ddmtodxm">\r
1080     <processor name="tile_3.magic"/>\r
1081     <txbuf name="tile_3.ddm"/>\r
1082     <hw_channel name="tile_3.dma"/>\r
1083     <hw_channel name="tile_3.ahb1"/>\r
1084     <chbuf name="tile_3.dxm"/>\r
1085     <configuration name="delay" value="0"/>\r
1086     <configuration name="cycles" value="8"/>\r
1087   </writepath>\r
1088 \r
1089   <readpath name="tile_3.ddmfromdxm">\r
1090     <processor name="tile_3.magic"/>\r
1091     <chbuf name="tile_3.dxm"/>\r
1092     <hw_channel name="tile_3.ahb1"/>\r
1093     <hw_channel name="tile_3.dma"/>\r
1094     <rxbuf name="tile_3.ddm"/>\r
1095     <configuration name="delay" value="0"/>\r
1096     <configuration name="cycles" value="8"/>\r
1097   </readpath>\r
1098 \r
1099   <!-- tile_3 ARM inter-tile communication paths -->\r
1100   <writepath name="tile_3.rdmtodnp_0">\r
1101     <processor name="tile_3.arm"/>\r
1102     <txbuf name="tile_3.rdm"/>\r
1103     <hw_channel name="tile_3.ahb0"/>\r
1104     <hw_channel name="tile_3.dnp"/>\r
1105     <hw_channel name="tile_0.dnp"/>\r
1106     <chbuf name="tile_0.dxm"/>\r
1107   </writepath>\r
1108 \r
1109   <writepath name="tile_3.rdmtodnp_1">\r
1110     <processor name="tile_3.arm"/>\r
1111     <txbuf name="tile_3.rdm"/>\r
1112     <hw_channel name="tile_3.ahb0"/>\r
1113     <hw_channel name="tile_3.dnp"/>\r
1114     <hw_channel name="tile_1.dnp"/>\r
1115     <chbuf name="tile_1.dxm"/>\r
1116   </writepath>\r
1117 \r
1118   <writepath name="tile_3.rdmtodnp_2">\r
1119     <processor name="tile_3.arm"/>\r
1120     <txbuf name="tile_3.rdm"/>\r
1121     <hw_channel name="tile_3.ahb0"/>\r
1122     <hw_channel name="tile_3.dnp"/>\r
1123     <hw_channel name="tile_2.dnp"/>\r
1124     <chbuf name="tile_2.dxm"/>\r
1125   </writepath>\r
1126 \r
1127   <writepath name="tile_3.rdmtodnp_4">\r
1128     <processor name="tile_3.arm"/>\r
1129     <txbuf name="tile_3.rdm"/>\r
1130     <hw_channel name="tile_3.ahb0"/>\r
1131     <hw_channel name="tile_3.dnp"/>\r
1132     <hw_channel name="tile_4.dnp"/>\r
1133     <chbuf name="tile_4.dxm"/>\r
1134   </writepath>\r
1135 \r
1136   <writepath name="tile_3.rdmtodnp_5">\r
1137     <processor name="tile_3.arm"/>\r
1138     <txbuf name="tile_3.rdm"/>\r
1139     <hw_channel name="tile_3.ahb0"/>\r
1140     <hw_channel name="tile_3.dnp"/>\r
1141     <hw_channel name="tile_5.dnp"/>\r
1142     <chbuf name="tile_5.dxm"/>\r
1143   </writepath>\r
1144 \r
1145   <writepath name="tile_3.rdmtodnp_6">\r
1146     <processor name="tile_3.arm"/>\r
1147     <txbuf name="tile_3.rdm"/>\r
1148     <hw_channel name="tile_3.ahb0"/>\r
1149     <hw_channel name="tile_3.dnp"/>\r
1150     <hw_channel name="tile_6.dnp"/>\r
1151     <chbuf name="tile_6.dxm"/>\r
1152   </writepath>\r
1153 \r
1154   <writepath name="tile_3.rdmtodnp_7">\r
1155     <processor name="tile_3.arm"/>\r
1156     <txbuf name="tile_3.rdm"/>\r
1157     <hw_channel name="tile_3.ahb0"/>\r
1158     <hw_channel name="tile_3.dnp"/>\r
1159     <hw_channel name="tile_7.dnp"/>\r
1160     <chbuf name="tile_7.dxm"/>\r
1161   </writepath>\r
1162 \r
1163   <!-- tile_3 DSP inter-tile communication paths -->\r
1164   <writepath name="tile_3.ddmtodnp_0">\r
1165     <processor name="tile_3.magic"/>\r
1166     <txbuf name="tile_3.ddm"/>\r
1167     <hw_channel name="tile_3.ahb0"/>\r
1168     <hw_channel name="tile_3.dnp"/>\r
1169     <hw_channel name="tile_0.dnp"/>\r
1170     <chbuf name="tile_0.dxm"/>\r
1171   </writepath>\r
1172 \r
1173   <writepath name="tile_3.ddmtodnp_1">\r
1174     <processor name="tile_3.magic"/>\r
1175     <txbuf name="tile_3.ddm"/>\r
1176     <hw_channel name="tile_3.ahb0"/>\r
1177     <hw_channel name="tile_3.dnp"/>\r
1178     <hw_channel name="tile_1.dnp"/>\r
1179     <chbuf name="tile_1.dxm"/>\r
1180   </writepath>\r
1181 \r
1182   <writepath name="tile_3.ddmtodnp_2">\r
1183     <processor name="tile_3.magic"/>\r
1184     <txbuf name="tile_3.ddm"/>\r
1185     <hw_channel name="tile_3.ahb0"/>\r
1186     <hw_channel name="tile_3.dnp"/>\r
1187     <hw_channel name="tile_2.dnp"/>\r
1188     <chbuf name="tile_2.dxm"/>\r
1189   </writepath>\r
1190 \r
1191   <writepath name="tile_3.ddmtodnp_4">\r
1192     <processor name="tile_3.magic"/>\r
1193     <txbuf name="tile_3.ddm"/>\r
1194     <hw_channel name="tile_3.ahb0"/>\r
1195     <hw_channel name="tile_3.dnp"/>\r
1196     <hw_channel name="tile_4.dnp"/>\r
1197     <chbuf name="tile_4.dxm"/>\r
1198   </writepath>\r
1199 \r
1200   <writepath name="tile_3.ddmtodnp_5">\r
1201     <processor name="tile_3.magic"/>\r
1202     <txbuf name="tile_3.ddm"/>\r
1203     <hw_channel name="tile_3.ahb0"/>\r
1204     <hw_channel name="tile_3.dnp"/>\r
1205     <hw_channel name="tile_5.dnp"/>\r
1206     <chbuf name="tile_5.dxm"/>\r
1207   </writepath>\r
1208 \r
1209   <writepath name="tile_3.ddmtodnp_6">\r
1210     <processor name="tile_3.magic"/>\r
1211     <txbuf name="tile_3.ddm"/>\r
1212     <hw_channel name="tile_3.ahb0"/>\r
1213     <hw_channel name="tile_3.dnp"/>\r
1214     <hw_channel name="tile_6.dnp"/>\r
1215     <chbuf name="tile_6.dxm"/>\r
1216   </writepath>\r
1217 \r
1218   <writepath name="tile_3.ddmtodnp_7">\r
1219     <processor name="tile_3.magic"/>\r
1220     <txbuf name="tile_3.ddm"/>\r
1221     <hw_channel name="tile_3.ahb0"/>\r
1222     <hw_channel name="tile_3.dnp"/>\r
1223     <hw_channel name="tile_7.dnp"/>\r
1224     <chbuf name="tile_7.dxm"/>\r
1225   </writepath>\r
1226 \r
1227 \r
1228   <!--*****************************************************************-->\r
1229   <!-- tile_4 communication paths -->\r
1230   <!--*****************************************************************-->\r
1231   <writepath name="tile_4.rdmtodxm">\r
1232     <processor name="tile_4.arm"/>\r
1233     <txbuf name="tile_4.rdm"/>\r
1234     <hw_channel name="tile_4.armbus"/>\r
1235     <hw_channel name="tile_4.ahb1"/>\r
1236     <chbuf name="tile_4.dxm"/>\r
1237     <configuration name="delay" value="0"/>\r
1238     <configuration name="cycles" value="8"/>\r
1239   </writepath>\r
1240 \r
1241   <readpath name="tile_4.rdmfromdxm">\r
1242     <processor name="tile_4.arm"/>\r
1243     <chbuf name="tile_4.dxm"/>\r
1244     <hw_channel name="tile_4.ahb1"/>\r
1245     <hw_channel name="tile_4.armbus"/>\r
1246     <rxbuf name="tile_4.rdm"/>\r
1247     <configuration name="delay" value="0"/>\r
1248     <configuration name="cycles" value="8"/>\r
1249   </readpath>\r
1250 \r
1251   <writepath name="tile_4.rdmtordm">\r
1252     <processor name="tile_4.arm"/>\r
1253     <txbuf name="tile_4.rdm"/>\r
1254     <hw_channel name="tile_4.armbus"/>\r
1255     <chbuf name="tile_4.rdm"/>\r
1256     <configuration name="delay" value="0"/>\r
1257     <configuration name="cycles" value="8"/>\r
1258   </writepath>\r
1259 \r
1260   <readpath name="tile_4.rdmfromrdm">\r
1261     <processor name="tile_4.arm"/>\r
1262     <chbuf name="tile_4.rdm"/>\r
1263     <hw_channel name="tile_4.armbus"/>\r
1264     <rxbuf name="tile_4.rdm"/>\r
1265     <configuration name="delay" value="0"/>\r
1266     <configuration name="cycles" value="8"/>\r
1267   </readpath>\r
1268 \r
1269   <writepath name="tile_4.ddmtoddm">\r
1270     <processor name="tile_4.magic"/>\r
1271     <txbuf name="tile_4.ddm"/>\r
1272     <hw_channel name="tile_4.magicbus"/>\r
1273     <chbuf name="tile_4.ddm"/>\r
1274     <configuration name="delay" value="0"/>\r
1275     <configuration name="cycles" value="8"/>\r
1276   </writepath>\r
1277 \r
1278   <readpath name="tile_4.ddmfromddm">\r
1279     <processor name="tile_4.magic"/>\r
1280     <chbuf name="tile_4.ddm"/>\r
1281     <hw_channel name="tile_4.magicbus"/>\r
1282     <rxbuf name="tile_4.ddm"/>\r
1283     <configuration name="delay" value="0"/>\r
1284     <configuration name="cycles" value="8"/>\r
1285   </readpath>\r
1286 \r
1287   <writepath name="tile_4.ddmtodxm">\r
1288     <processor name="tile_4.magic"/>\r
1289     <txbuf name="tile_4.ddm"/>\r
1290     <hw_channel name="tile_4.dma"/>\r
1291     <hw_channel name="tile_4.ahb1"/>\r
1292     <chbuf name="tile_4.dxm"/>\r
1293     <configuration name="delay" value="0"/>\r
1294     <configuration name="cycles" value="8"/>\r
1295   </writepath>\r
1296 \r
1297   <readpath name="tile_4.ddmfromdxm">\r
1298     <processor name="tile_4.magic"/>\r
1299     <chbuf name="tile_4.dxm"/>\r
1300     <hw_channel name="tile_4.ahb1"/>\r
1301     <hw_channel name="tile_4.dma"/>\r
1302     <rxbuf name="tile_4.ddm"/>\r
1303     <configuration name="delay" value="0"/>\r
1304     <configuration name="cycles" value="8"/>\r
1305   </readpath>\r
1306 \r
1307   <!-- tile_4 ARM inter-tile communication paths -->\r
1308   <writepath name="tile_4.rdmtodnp_0">\r
1309     <processor name="tile_4.arm"/>\r
1310     <txbuf name="tile_4.rdm"/>\r
1311     <hw_channel name="tile_4.ahb0"/>\r
1312     <hw_channel name="tile_4.dnp"/>\r
1313     <hw_channel name="tile_0.dnp"/>\r
1314     <chbuf name="tile_0.dxm"/>\r
1315   </writepath>\r
1316 \r
1317   <writepath name="tile_4.rdmtodnp_1">\r
1318     <processor name="tile_4.arm"/>\r
1319     <txbuf name="tile_4.rdm"/>\r
1320     <hw_channel name="tile_4.ahb0"/>\r
1321     <hw_channel name="tile_4.dnp"/>\r
1322     <hw_channel name="tile_1.dnp"/>\r
1323     <chbuf name="tile_1.dxm"/>\r
1324   </writepath>\r
1325 \r
1326   <writepath name="tile_4.rdmtodnp_2">\r
1327     <processor name="tile_4.arm"/>\r
1328     <txbuf name="tile_4.rdm"/>\r
1329     <hw_channel name="tile_4.ahb0"/>\r
1330     <hw_channel name="tile_4.dnp"/>\r
1331     <hw_channel name="tile_2.dnp"/>\r
1332     <chbuf name="tile_2.dxm"/>\r
1333   </writepath>\r
1334 \r
1335   <writepath name="tile_4.rdmtodnp_3">\r
1336     <processor name="tile_4.arm"/>\r
1337     <txbuf name="tile_4.rdm"/>\r
1338     <hw_channel name="tile_4.ahb0"/>\r
1339     <hw_channel name="tile_4.dnp"/>\r
1340     <hw_channel name="tile_3.dnp"/>\r
1341     <chbuf name="tile_3.dxm"/>\r
1342   </writepath>\r
1343 \r
1344   <writepath name="tile_4.rdmtodnp_5">\r
1345     <processor name="tile_4.arm"/>\r
1346     <txbuf name="tile_4.rdm"/>\r
1347     <hw_channel name="tile_4.ahb0"/>\r
1348     <hw_channel name="tile_4.dnp"/>\r
1349     <hw_channel name="tile_5.dnp"/>\r
1350     <chbuf name="tile_5.dxm"/>\r
1351   </writepath>\r
1352 \r
1353   <writepath name="tile_4.rdmtodnp_6">\r
1354     <processor name="tile_4.arm"/>\r
1355     <txbuf name="tile_4.rdm"/>\r
1356     <hw_channel name="tile_4.ahb0"/>\r
1357     <hw_channel name="tile_4.dnp"/>\r
1358     <hw_channel name="tile_6.dnp"/>\r
1359     <chbuf name="tile_6.dxm"/>\r
1360   </writepath>\r
1361 \r
1362   <writepath name="tile_4.rdmtodnp_7">\r
1363     <processor name="tile_4.arm"/>\r
1364     <txbuf name="tile_4.rdm"/>\r
1365     <hw_channel name="tile_4.ahb0"/>\r
1366     <hw_channel name="tile_4.dnp"/>\r
1367     <hw_channel name="tile_7.dnp"/>\r
1368     <chbuf name="tile_7.dxm"/>\r
1369   </writepath>\r
1370 \r
1371   <!-- tile_4 DSP inter-tile communication paths -->\r
1372   <writepath name="tile_4.ddmtodnp_0">\r
1373     <processor name="tile_4.magic"/>\r
1374     <txbuf name="tile_4.ddm"/>\r
1375     <hw_channel name="tile_4.ahb0"/>\r
1376     <hw_channel name="tile_4.dnp"/>\r
1377     <hw_channel name="tile_0.dnp"/>\r
1378     <chbuf name="tile_0.dxm"/>\r
1379   </writepath>\r
1380 \r
1381   <writepath name="tile_4.ddmtodnp_1">\r
1382     <processor name="tile_4.magic"/>\r
1383     <txbuf name="tile_4.ddm"/>\r
1384     <hw_channel name="tile_4.ahb0"/>\r
1385     <hw_channel name="tile_4.dnp"/>\r
1386     <hw_channel name="tile_1.dnp"/>\r
1387     <chbuf name="tile_1.dxm"/>\r
1388   </writepath>\r
1389 \r
1390   <writepath name="tile_4.ddmtodnp_2">\r
1391     <processor name="tile_4.magic"/>\r
1392     <txbuf name="tile_4.ddm"/>\r
1393     <hw_channel name="tile_4.ahb0"/>\r
1394     <hw_channel name="tile_4.dnp"/>\r
1395     <hw_channel name="tile_2.dnp"/>\r
1396     <chbuf name="tile_2.dxm"/>\r
1397   </writepath>\r
1398 \r
1399   <writepath name="tile_4.ddmtodnp_3">\r
1400     <processor name="tile_4.magic"/>\r
1401     <txbuf name="tile_4.ddm"/>\r
1402     <hw_channel name="tile_4.ahb0"/>\r
1403     <hw_channel name="tile_4.dnp"/>\r
1404     <hw_channel name="tile_3.dnp"/>\r
1405     <chbuf name="tile_3.dxm"/>\r
1406   </writepath>\r
1407 \r
1408   <writepath name="tile_4.ddmtodnp_5">\r
1409     <processor name="tile_4.magic"/>\r
1410     <txbuf name="tile_4.ddm"/>\r
1411     <hw_channel name="tile_4.ahb0"/>\r
1412     <hw_channel name="tile_4.dnp"/>\r
1413     <hw_channel name="tile_5.dnp"/>\r
1414     <chbuf name="tile_5.dxm"/>\r
1415   </writepath>\r
1416 \r
1417   <writepath name="tile_4.ddmtodnp_6">\r
1418     <processor name="tile_4.magic"/>\r
1419     <txbuf name="tile_4.ddm"/>\r
1420     <hw_channel name="tile_4.ahb0"/>\r
1421     <hw_channel name="tile_4.dnp"/>\r
1422     <hw_channel name="tile_6.dnp"/>\r
1423     <chbuf name="tile_6.dxm"/>\r
1424   </writepath>\r
1425 \r
1426   <writepath name="tile_4.ddmtodnp_7">\r
1427     <processor name="tile_4.magic"/>\r
1428     <txbuf name="tile_4.ddm"/>\r
1429     <hw_channel name="tile_4.ahb0"/>\r
1430     <hw_channel name="tile_4.dnp"/>\r
1431     <hw_channel name="tile_7.dnp"/>\r
1432     <chbuf name="tile_7.dxm"/>\r
1433   </writepath>\r
1434 \r
1435 \r
1436   <!--*****************************************************************-->\r
1437   <!-- tile_5 communication paths -->\r
1438   <!--*****************************************************************-->\r
1439   <writepath name="tile_5.rdmtodxm">\r
1440     <processor name="tile_5.arm"/>\r
1441     <txbuf name="tile_5.rdm"/>\r
1442     <hw_channel name="tile_5.armbus"/>\r
1443     <hw_channel name="tile_5.ahb1"/>\r
1444     <chbuf name="tile_5.dxm"/>\r
1445     <configuration name="delay" value="0"/>\r
1446     <configuration name="cycles" value="8"/>\r
1447   </writepath>\r
1448 \r
1449   <readpath name="tile_5.rdmfromdxm">\r
1450     <processor name="tile_5.arm"/>\r
1451     <chbuf name="tile_5.dxm"/>\r
1452     <hw_channel name="tile_5.ahb1"/>\r
1453     <hw_channel name="tile_5.armbus"/>\r
1454     <rxbuf name="tile_5.rdm"/>\r
1455     <configuration name="delay" value="0"/>\r
1456     <configuration name="cycles" value="8"/>\r
1457   </readpath>\r
1458 \r
1459   <writepath name="tile_5.rdmtordm">\r
1460     <processor name="tile_5.arm"/>\r
1461     <txbuf name="tile_5.rdm"/>\r
1462     <hw_channel name="tile_5.armbus"/>\r
1463     <chbuf name="tile_5.rdm"/>\r
1464     <configuration name="delay" value="0"/>\r
1465     <configuration name="cycles" value="8"/>\r
1466   </writepath>\r
1467 \r
1468   <readpath name="tile_5.rdmfromrdm">\r
1469     <processor name="tile_5.arm"/>\r
1470     <chbuf name="tile_5.rdm"/>\r
1471     <hw_channel name="tile_5.armbus"/>\r
1472     <rxbuf name="tile_5.rdm"/>\r
1473     <configuration name="delay" value="0"/>\r
1474     <configuration name="cycles" value="8"/>\r
1475   </readpath>\r
1476 \r
1477   <writepath name="tile_5.ddmtoddm">\r
1478     <processor name="tile_5.magic"/>\r
1479     <txbuf name="tile_5.ddm"/>\r
1480     <hw_channel name="tile_5.magicbus"/>\r
1481     <chbuf name="tile_5.ddm"/>\r
1482     <configuration name="delay" value="0"/>\r
1483     <configuration name="cycles" value="8"/>\r
1484   </writepath>\r
1485 \r
1486   <readpath name="tile_5.ddmfromddm">\r
1487     <processor name="tile_5.magic"/>\r
1488     <chbuf name="tile_5.ddm"/>\r
1489     <hw_channel name="tile_5.magicbus"/>\r
1490     <rxbuf name="tile_5.ddm"/>\r
1491     <configuration name="delay" value="0"/>\r
1492     <configuration name="cycles" value="8"/>\r
1493   </readpath>\r
1494 \r
1495   <writepath name="tile_5.ddmtodxm">\r
1496     <processor name="tile_5.magic"/>\r
1497     <txbuf name="tile_5.ddm"/>\r
1498     <hw_channel name="tile_5.dma"/>\r
1499     <hw_channel name="tile_5.ahb1"/>\r
1500     <chbuf name="tile_5.dxm"/>\r
1501     <configuration name="delay" value="0"/>\r
1502     <configuration name="cycles" value="8"/>\r
1503   </writepath>\r
1504 \r
1505   <readpath name="tile_5.ddmfromdxm">\r
1506     <processor name="tile_5.magic"/>\r
1507     <chbuf name="tile_5.dxm"/>\r
1508     <hw_channel name="tile_5.ahb1"/>\r
1509     <hw_channel name="tile_5.dma"/>\r
1510     <rxbuf name="tile_5.ddm"/>\r
1511     <configuration name="delay" value="0"/>\r
1512     <configuration name="cycles" value="8"/>\r
1513   </readpath>\r
1514 \r
1515   <!-- tile_5 ARM inter-tile communication paths -->\r
1516   <writepath name="tile_5.rdmtodnp_0">\r
1517     <processor name="tile_5.arm"/>\r
1518     <txbuf name="tile_5.rdm"/>\r
1519     <hw_channel name="tile_5.ahb0"/>\r
1520     <hw_channel name="tile_5.dnp"/>\r
1521     <hw_channel name="tile_0.dnp"/>\r
1522     <chbuf name="tile_0.dxm"/>\r
1523   </writepath>\r
1524 \r
1525   <writepath name="tile_5.rdmtodnp_1">\r
1526     <processor name="tile_5.arm"/>\r
1527     <txbuf name="tile_5.rdm"/>\r
1528     <hw_channel name="tile_5.ahb0"/>\r
1529     <hw_channel name="tile_5.dnp"/>\r
1530     <hw_channel name="tile_1.dnp"/>\r
1531     <chbuf name="tile_1.dxm"/>\r
1532   </writepath>\r
1533 \r
1534   <writepath name="tile_5.rdmtodnp_2">\r
1535     <processor name="tile_5.arm"/>\r
1536     <txbuf name="tile_5.rdm"/>\r
1537     <hw_channel name="tile_5.ahb0"/>\r
1538     <hw_channel name="tile_5.dnp"/>\r
1539     <hw_channel name="tile_2.dnp"/>\r
1540     <chbuf name="tile_2.dxm"/>\r
1541   </writepath>\r
1542 \r
1543   <writepath name="tile_5.rdmtodnp_3">\r
1544     <processor name="tile_5.arm"/>\r
1545     <txbuf name="tile_5.rdm"/>\r
1546     <hw_channel name="tile_5.ahb0"/>\r
1547     <hw_channel name="tile_5.dnp"/>\r
1548     <hw_channel name="tile_3.dnp"/>\r
1549     <chbuf name="tile_3.dxm"/>\r
1550   </writepath>\r
1551 \r
1552   <writepath name="tile_5.rdmtodnp_4">\r
1553     <processor name="tile_5.arm"/>\r
1554     <txbuf name="tile_5.rdm"/>\r
1555     <hw_channel name="tile_5.ahb0"/>\r
1556     <hw_channel name="tile_5.dnp"/>\r
1557     <hw_channel name="tile_4.dnp"/>\r
1558     <chbuf name="tile_4.dxm"/>\r
1559   </writepath>\r
1560 \r
1561   <writepath name="tile_5.rdmtodnp_6">\r
1562     <processor name="tile_5.arm"/>\r
1563     <txbuf name="tile_5.rdm"/>\r
1564     <hw_channel name="tile_5.ahb0"/>\r
1565     <hw_channel name="tile_5.dnp"/>\r
1566     <hw_channel name="tile_6.dnp"/>\r
1567     <chbuf name="tile_6.dxm"/>\r
1568   </writepath>\r
1569 \r
1570   <writepath name="tile_5.rdmtodnp_7">\r
1571     <processor name="tile_5.arm"/>\r
1572     <txbuf name="tile_5.rdm"/>\r
1573     <hw_channel name="tile_5.ahb0"/>\r
1574     <hw_channel name="tile_5.dnp"/>\r
1575     <hw_channel name="tile_7.dnp"/>\r
1576     <chbuf name="tile_7.dxm"/>\r
1577   </writepath>\r
1578 \r
1579   <!-- tile_5 DSP inter-tile communication paths -->\r
1580   <writepath name="tile_5.ddmtodnp_0">\r
1581     <processor name="tile_5.magic"/>\r
1582     <txbuf name="tile_5.ddm"/>\r
1583     <hw_channel name="tile_5.ahb0"/>\r
1584     <hw_channel name="tile_5.dnp"/>\r
1585     <hw_channel name="tile_0.dnp"/>\r
1586     <chbuf name="tile_0.dxm"/>\r
1587   </writepath>\r
1588 \r
1589   <writepath name="tile_5.ddmtodnp_1">\r
1590     <processor name="tile_5.magic"/>\r
1591     <txbuf name="tile_5.ddm"/>\r
1592     <hw_channel name="tile_5.ahb0"/>\r
1593     <hw_channel name="tile_5.dnp"/>\r
1594     <hw_channel name="tile_1.dnp"/>\r
1595     <chbuf name="tile_1.dxm"/>\r
1596   </writepath>\r
1597 \r
1598   <writepath name="tile_5.ddmtodnp_2">\r
1599     <processor name="tile_5.magic"/>\r
1600     <txbuf name="tile_5.ddm"/>\r
1601     <hw_channel name="tile_5.ahb0"/>\r
1602     <hw_channel name="tile_5.dnp"/>\r
1603     <hw_channel name="tile_2.dnp"/>\r
1604     <chbuf name="tile_2.dxm"/>\r
1605   </writepath>\r
1606 \r
1607   <writepath name="tile_5.ddmtodnp_3">\r
1608     <processor name="tile_5.magic"/>\r
1609     <txbuf name="tile_5.ddm"/>\r
1610     <hw_channel name="tile_5.ahb0"/>\r
1611     <hw_channel name="tile_5.dnp"/>\r
1612     <hw_channel name="tile_3.dnp"/>\r
1613     <chbuf name="tile_3.dxm"/>\r
1614   </writepath>\r
1615 \r
1616   <writepath name="tile_5.ddmtodnp_4">\r
1617     <processor name="tile_5.magic"/>\r
1618     <txbuf name="tile_5.ddm"/>\r
1619     <hw_channel name="tile_5.ahb0"/>\r
1620     <hw_channel name="tile_5.dnp"/>\r
1621     <hw_channel name="tile_4.dnp"/>\r
1622     <chbuf name="tile_4.dxm"/>\r
1623   </writepath>\r
1624 \r
1625   <writepath name="tile_5.ddmtodnp_6">\r
1626     <processor name="tile_5.magic"/>\r
1627     <txbuf name="tile_5.ddm"/>\r
1628     <hw_channel name="tile_5.ahb0"/>\r
1629     <hw_channel name="tile_5.dnp"/>\r
1630     <hw_channel name="tile_6.dnp"/>\r
1631     <chbuf name="tile_6.dxm"/>\r
1632   </writepath>\r
1633 \r
1634   <writepath name="tile_5.ddmtodnp_7">\r
1635     <processor name="tile_5.magic"/>\r
1636     <txbuf name="tile_5.ddm"/>\r
1637     <hw_channel name="tile_5.ahb0"/>\r
1638     <hw_channel name="tile_5.dnp"/>\r
1639     <hw_channel name="tile_7.dnp"/>\r
1640     <chbuf name="tile_7.dxm"/>\r
1641   </writepath>\r
1642 \r
1643 \r
1644   <!--*****************************************************************-->\r
1645   <!-- tile_6 communication paths -->\r
1646   <!--*****************************************************************-->\r
1647   <writepath name="tile_6.rdmtodxm">\r
1648     <processor name="tile_6.arm"/>\r
1649     <txbuf name="tile_6.rdm"/>\r
1650     <hw_channel name="tile_6.armbus"/>\r
1651     <hw_channel name="tile_6.ahb1"/>\r
1652     <chbuf name="tile_6.dxm"/>\r
1653     <configuration name="delay" value="0"/>\r
1654     <configuration name="cycles" value="8"/>\r
1655   </writepath>\r
1656 \r
1657   <readpath name="tile_6.rdmfromdxm">\r
1658     <processor name="tile_6.arm"/>\r
1659     <chbuf name="tile_6.dxm"/>\r
1660     <hw_channel name="tile_6.ahb1"/>\r
1661     <hw_channel name="tile_6.armbus"/>\r
1662     <rxbuf name="tile_6.rdm"/>\r
1663     <configuration name="delay" value="0"/>\r
1664     <configuration name="cycles" value="8"/>\r
1665   </readpath>\r
1666 \r
1667   <writepath name="tile_6.rdmtordm">\r
1668     <processor name="tile_6.arm"/>\r
1669     <txbuf name="tile_6.rdm"/>\r
1670     <hw_channel name="tile_6.armbus"/>\r
1671     <chbuf name="tile_6.rdm"/>\r
1672     <configuration name="delay" value="0"/>\r
1673     <configuration name="cycles" value="8"/>\r
1674   </writepath>\r
1675 \r
1676   <readpath name="tile_6.rdmfromrdm">\r
1677     <processor name="tile_6.arm"/>\r
1678     <chbuf name="tile_6.rdm"/>\r
1679     <hw_channel name="tile_6.armbus"/>\r
1680     <rxbuf name="tile_6.rdm"/>\r
1681     <configuration name="delay" value="0"/>\r
1682     <configuration name="cycles" value="8"/>\r
1683   </readpath>\r
1684 \r
1685   <writepath name="tile_6.ddmtoddm">\r
1686     <processor name="tile_6.magic"/>\r
1687     <txbuf name="tile_6.ddm"/>\r
1688     <hw_channel name="tile_6.magicbus"/>\r
1689     <chbuf name="tile_6.ddm"/>\r
1690     <configuration name="delay" value="0"/>\r
1691     <configuration name="cycles" value="8"/>\r
1692   </writepath>\r
1693 \r
1694   <readpath name="tile_6.ddmfromddm">\r
1695     <processor name="tile_6.magic"/>\r
1696     <chbuf name="tile_6.ddm"/>\r
1697     <hw_channel name="tile_6.magicbus"/>\r
1698     <rxbuf name="tile_6.ddm"/>\r
1699     <configuration name="delay" value="0"/>\r
1700     <configuration name="cycles" value="8"/>\r
1701   </readpath>\r
1702 \r
1703   <writepath name="tile_6.ddmtodxm">\r
1704     <processor name="tile_6.magic"/>\r
1705     <txbuf name="tile_6.ddm"/>\r
1706     <hw_channel name="tile_6.dma"/>\r
1707     <hw_channel name="tile_6.ahb1"/>\r
1708     <chbuf name="tile_6.dxm"/>\r
1709     <configuration name="delay" value="0"/>\r
1710     <configuration name="cycles" value="8"/>\r
1711   </writepath>\r
1712 \r
1713   <readpath name="tile_6.ddmfromdxm">\r
1714     <processor name="tile_6.magic"/>\r
1715     <chbuf name="tile_6.dxm"/>\r
1716     <hw_channel name="tile_6.ahb1"/>\r
1717     <hw_channel name="tile_6.dma"/>\r
1718     <rxbuf name="tile_6.ddm"/>\r
1719     <configuration name="delay" value="0"/>\r
1720     <configuration name="cycles" value="8"/>\r
1721   </readpath>\r
1722 \r
1723   <!-- tile_6 ARM inter-tile communication paths -->\r
1724   <writepath name="tile_6.rdmtodnp_0">\r
1725     <processor name="tile_6.arm"/>\r
1726     <txbuf name="tile_6.rdm"/>\r
1727     <hw_channel name="tile_6.ahb0"/>\r
1728     <hw_channel name="tile_6.dnp"/>\r
1729     <hw_channel name="tile_0.dnp"/>\r
1730     <chbuf name="tile_0.dxm"/>\r
1731   </writepath>\r
1732 \r
1733   <writepath name="tile_6.rdmtodnp_1">\r
1734     <processor name="tile_6.arm"/>\r
1735     <txbuf name="tile_6.rdm"/>\r
1736     <hw_channel name="tile_6.ahb0"/>\r
1737     <hw_channel name="tile_6.dnp"/>\r
1738     <hw_channel name="tile_1.dnp"/>\r
1739     <chbuf name="tile_1.dxm"/>\r
1740   </writepath>\r
1741 \r
1742   <writepath name="tile_6.rdmtodnp_2">\r
1743     <processor name="tile_6.arm"/>\r
1744     <txbuf name="tile_6.rdm"/>\r
1745     <hw_channel name="tile_6.ahb0"/>\r
1746     <hw_channel name="tile_6.dnp"/>\r
1747     <hw_channel name="tile_2.dnp"/>\r
1748     <chbuf name="tile_2.dxm"/>\r
1749   </writepath>\r
1750 \r
1751   <writepath name="tile_6.rdmtodnp_3">\r
1752     <processor name="tile_6.arm"/>\r
1753     <txbuf name="tile_6.rdm"/>\r
1754     <hw_channel name="tile_6.ahb0"/>\r
1755     <hw_channel name="tile_6.dnp"/>\r
1756     <hw_channel name="tile_3.dnp"/>\r
1757     <chbuf name="tile_3.dxm"/>\r
1758   </writepath>\r
1759 \r
1760   <writepath name="tile_6.rdmtodnp_4">\r
1761     <processor name="tile_6.arm"/>\r
1762     <txbuf name="tile_6.rdm"/>\r
1763     <hw_channel name="tile_6.ahb0"/>\r
1764     <hw_channel name="tile_6.dnp"/>\r
1765     <hw_channel name="tile_4.dnp"/>\r
1766     <chbuf name="tile_4.dxm"/>\r
1767   </writepath>\r
1768 \r
1769   <writepath name="tile_6.rdmtodnp_5">\r
1770     <processor name="tile_6.arm"/>\r
1771     <txbuf name="tile_6.rdm"/>\r
1772     <hw_channel name="tile_6.ahb0"/>\r
1773     <hw_channel name="tile_6.dnp"/>\r
1774     <hw_channel name="tile_5.dnp"/>\r
1775     <chbuf name="tile_5.dxm"/>\r
1776   </writepath>\r
1777 \r
1778   <writepath name="tile_6.rdmtodnp_7">\r
1779     <processor name="tile_6.arm"/>\r
1780     <txbuf name="tile_6.rdm"/>\r
1781     <hw_channel name="tile_6.ahb0"/>\r
1782     <hw_channel name="tile_6.dnp"/>\r
1783     <hw_channel name="tile_7.dnp"/>\r
1784     <chbuf name="tile_7.dxm"/>\r
1785   </writepath>\r
1786 \r
1787   <!-- tile_6 DSP inter-tile communication paths -->\r
1788   <writepath name="tile_6.ddmtodnp_0">\r
1789     <processor name="tile_6.magic"/>\r
1790     <txbuf name="tile_6.ddm"/>\r
1791     <hw_channel name="tile_6.ahb0"/>\r
1792     <hw_channel name="tile_6.dnp"/>\r
1793     <hw_channel name="tile_0.dnp"/>\r
1794     <chbuf name="tile_0.dxm"/>\r
1795   </writepath>\r
1796 \r
1797   <writepath name="tile_6.ddmtodnp_1">\r
1798     <processor name="tile_6.magic"/>\r
1799     <txbuf name="tile_6.ddm"/>\r
1800     <hw_channel name="tile_6.ahb0"/>\r
1801     <hw_channel name="tile_6.dnp"/>\r
1802     <hw_channel name="tile_1.dnp"/>\r
1803     <chbuf name="tile_1.dxm"/>\r
1804   </writepath>\r
1805 \r
1806   <writepath name="tile_6.ddmtodnp_2">\r
1807     <processor name="tile_6.magic"/>\r
1808     <txbuf name="tile_6.ddm"/>\r
1809     <hw_channel name="tile_6.ahb0"/>\r
1810     <hw_channel name="tile_6.dnp"/>\r
1811     <hw_channel name="tile_2.dnp"/>\r
1812     <chbuf name="tile_2.dxm"/>\r
1813   </writepath>\r
1814 \r
1815   <writepath name="tile_6.ddmtodnp_3">\r
1816     <processor name="tile_6.magic"/>\r
1817     <txbuf name="tile_6.ddm"/>\r
1818     <hw_channel name="tile_6.ahb0"/>\r
1819     <hw_channel name="tile_6.dnp"/>\r
1820     <hw_channel name="tile_3.dnp"/>\r
1821     <chbuf name="tile_3.dxm"/>\r
1822   </writepath>\r
1823 \r
1824   <writepath name="tile_6.ddmtodnp_4">\r
1825     <processor name="tile_6.magic"/>\r
1826     <txbuf name="tile_6.ddm"/>\r
1827     <hw_channel name="tile_6.ahb0"/>\r
1828     <hw_channel name="tile_6.dnp"/>\r
1829     <hw_channel name="tile_4.dnp"/>\r
1830     <chbuf name="tile_4.dxm"/>\r
1831   </writepath>\r
1832 \r
1833   <writepath name="tile_6.ddmtodnp_5">\r
1834     <processor name="tile_6.magic"/>\r
1835     <txbuf name="tile_6.ddm"/>\r
1836     <hw_channel name="tile_6.ahb0"/>\r
1837     <hw_channel name="tile_6.dnp"/>\r
1838     <hw_channel name="tile_5.dnp"/>\r
1839     <chbuf name="tile_5.dxm"/>\r
1840   </writepath>\r
1841 \r
1842   <writepath name="tile_6.ddmtodnp_7">\r
1843     <processor name="tile_6.magic"/>\r
1844     <txbuf name="tile_6.ddm"/>\r
1845     <hw_channel name="tile_6.ahb0"/>\r
1846     <hw_channel name="tile_6.dnp"/>\r
1847     <hw_channel name="tile_7.dnp"/>\r
1848     <chbuf name="tile_7.dxm"/>\r
1849   </writepath>\r
1850 \r
1851 \r
1852   <!--*****************************************************************-->\r
1853   <!-- tile_7 communication paths -->\r
1854   <!--*****************************************************************-->\r
1855   <writepath name="tile_7.rdmtodxm">\r
1856     <processor name="tile_7.arm"/>\r
1857     <txbuf name="tile_7.rdm"/>\r
1858     <hw_channel name="tile_7.armbus"/>\r
1859     <hw_channel name="tile_7.ahb1"/>\r
1860     <chbuf name="tile_7.dxm"/>\r
1861     <configuration name="delay" value="0"/>\r
1862     <configuration name="cycles" value="8"/>\r
1863   </writepath>\r
1864 \r
1865   <readpath name="tile_7.rdmfromdxm">\r
1866     <processor name="tile_7.arm"/>\r
1867     <chbuf name="tile_7.dxm"/>\r
1868     <hw_channel name="tile_7.ahb1"/>\r
1869     <hw_channel name="tile_7.armbus"/>\r
1870     <rxbuf name="tile_7.rdm"/>\r
1871     <configuration name="delay" value="0"/>\r
1872     <configuration name="cycles" value="8"/>\r
1873   </readpath>\r
1874 \r
1875   <writepath name="tile_7.rdmtordm">\r
1876     <processor name="tile_7.arm"/>\r
1877     <txbuf name="tile_7.rdm"/>\r
1878     <hw_channel name="tile_7.armbus"/>\r
1879     <chbuf name="tile_7.rdm"/>\r
1880     <configuration name="delay" value="0"/>\r
1881     <configuration name="cycles" value="8"/>\r
1882   </writepath>\r
1883 \r
1884   <readpath name="tile_7.rdmfromrdm">\r
1885     <processor name="tile_7.arm"/>\r
1886     <chbuf name="tile_7.rdm"/>\r
1887     <hw_channel name="tile_7.armbus"/>\r
1888     <rxbuf name="tile_7.rdm"/>\r
1889     <configuration name="delay" value="0"/>\r
1890     <configuration name="cycles" value="8"/>\r
1891   </readpath>\r
1892 \r
1893   <writepath name="tile_7.ddmtoddm">\r
1894     <processor name="tile_7.magic"/>\r
1895     <txbuf name="tile_7.ddm"/>\r
1896     <hw_channel name="tile_7.magicbus"/>\r
1897     <chbuf name="tile_7.ddm"/>\r
1898     <configuration name="delay" value="0"/>\r
1899     <configuration name="cycles" value="8"/>\r
1900   </writepath>\r
1901 \r
1902   <readpath name="tile_7.ddmfromddm">\r
1903     <processor name="tile_7.magic"/>\r
1904     <chbuf name="tile_7.ddm"/>\r
1905     <hw_channel name="tile_7.magicbus"/>\r
1906     <rxbuf name="tile_7.ddm"/>\r
1907     <configuration name="delay" value="0"/>\r
1908     <configuration name="cycles" value="8"/>\r
1909   </readpath>\r
1910 \r
1911   <writepath name="tile_7.ddmtodxm">\r
1912     <processor name="tile_7.magic"/>\r
1913     <txbuf name="tile_7.ddm"/>\r
1914     <hw_channel name="tile_7.dma"/>\r
1915     <hw_channel name="tile_7.ahb1"/>\r
1916     <chbuf name="tile_7.dxm"/>\r
1917     <configuration name="delay" value="0"/>\r
1918     <configuration name="cycles" value="8"/>\r
1919   </writepath>\r
1920 \r
1921   <readpath name="tile_7.ddmfromdxm">\r
1922     <processor name="tile_7.magic"/>\r
1923     <chbuf name="tile_7.dxm"/>\r
1924     <hw_channel name="tile_7.ahb1"/>\r
1925     <hw_channel name="tile_7.dma"/>\r
1926     <rxbuf name="tile_7.ddm"/>\r
1927     <configuration name="delay" value="0"/>\r
1928     <configuration name="cycles" value="8"/>\r
1929   </readpath>\r
1930 \r
1931   <!-- tile_7 ARM inter-tile communication paths -->\r
1932   <writepath name="tile_7.rdmtodnp_0">\r
1933     <processor name="tile_7.arm"/>\r
1934     <txbuf name="tile_7.rdm"/>\r
1935     <hw_channel name="tile_7.ahb0"/>\r
1936     <hw_channel name="tile_7.dnp"/>\r
1937     <hw_channel name="tile_0.dnp"/>\r
1938     <chbuf name="tile_0.dxm"/>\r
1939   </writepath>\r
1940 \r
1941   <writepath name="tile_7.rdmtodnp_1">\r
1942     <processor name="tile_7.arm"/>\r
1943     <txbuf name="tile_7.rdm"/>\r
1944     <hw_channel name="tile_7.ahb0"/>\r
1945     <hw_channel name="tile_7.dnp"/>\r
1946     <hw_channel name="tile_1.dnp"/>\r
1947     <chbuf name="tile_1.dxm"/>\r
1948   </writepath>\r
1949 \r
1950   <writepath name="tile_7.rdmtodnp_2">\r
1951     <processor name="tile_7.arm"/>\r
1952     <txbuf name="tile_7.rdm"/>\r
1953     <hw_channel name="tile_7.ahb0"/>\r
1954     <hw_channel name="tile_7.dnp"/>\r
1955     <hw_channel name="tile_2.dnp"/>\r
1956     <chbuf name="tile_2.dxm"/>\r
1957   </writepath>\r
1958 \r
1959   <writepath name="tile_7.rdmtodnp_3">\r
1960     <processor name="tile_7.arm"/>\r
1961     <txbuf name="tile_7.rdm"/>\r
1962     <hw_channel name="tile_7.ahb0"/>\r
1963     <hw_channel name="tile_7.dnp"/>\r
1964     <hw_channel name="tile_3.dnp"/>\r
1965     <chbuf name="tile_3.dxm"/>\r
1966   </writepath>\r
1967 \r
1968   <writepath name="tile_7.rdmtodnp_4">\r
1969     <processor name="tile_7.arm"/>\r
1970     <txbuf name="tile_7.rdm"/>\r
1971     <hw_channel name="tile_7.ahb0"/>\r
1972     <hw_channel name="tile_7.dnp"/>\r
1973     <hw_channel name="tile_4.dnp"/>\r
1974     <chbuf name="tile_4.dxm"/>\r
1975   </writepath>\r
1976 \r
1977   <writepath name="tile_7.rdmtodnp_5">\r
1978     <processor name="tile_7.arm"/>\r
1979     <txbuf name="tile_7.rdm"/>\r
1980     <hw_channel name="tile_7.ahb0"/>\r
1981     <hw_channel name="tile_7.dnp"/>\r
1982     <hw_channel name="tile_5.dnp"/>\r
1983     <chbuf name="tile_5.dxm"/>\r
1984   </writepath>\r
1985 \r
1986   <writepath name="tile_7.rdmtodnp_6">\r
1987     <processor name="tile_7.arm"/>\r
1988     <txbuf name="tile_7.rdm"/>\r
1989     <hw_channel name="tile_7.ahb0"/>\r
1990     <hw_channel name="tile_7.dnp"/>\r
1991     <hw_channel name="tile_6.dnp"/>\r
1992     <chbuf name="tile_6.dxm"/>\r
1993   </writepath>\r
1994 \r
1995   <!-- tile_7 DSP inter-tile communication paths -->\r
1996   <writepath name="tile_7.ddmtodnp_0">\r
1997     <processor name="tile_7.magic"/>\r
1998     <txbuf name="tile_7.ddm"/>\r
1999     <hw_channel name="tile_7.ahb0"/>\r
2000     <hw_channel name="tile_7.dnp"/>\r
2001     <hw_channel name="tile_0.dnp"/>\r
2002     <chbuf name="tile_0.dxm"/>\r
2003   </writepath>\r
2004 \r
2005   <writepath name="tile_7.ddmtodnp_1">\r
2006     <processor name="tile_7.magic"/>\r
2007     <txbuf name="tile_7.ddm"/>\r
2008     <hw_channel name="tile_7.ahb0"/>\r
2009     <hw_channel name="tile_7.dnp"/>\r
2010     <hw_channel name="tile_1.dnp"/>\r
2011     <chbuf name="tile_1.dxm"/>\r
2012   </writepath>\r
2013 \r
2014   <writepath name="tile_7.ddmtodnp_2">\r
2015     <processor name="tile_7.magic"/>\r
2016     <txbuf name="tile_7.ddm"/>\r
2017     <hw_channel name="tile_7.ahb0"/>\r
2018     <hw_channel name="tile_7.dnp"/>\r
2019     <hw_channel name="tile_2.dnp"/>\r
2020     <chbuf name="tile_2.dxm"/>\r
2021   </writepath>\r
2022 \r
2023   <writepath name="tile_7.ddmtodnp_3">\r
2024     <processor name="tile_7.magic"/>\r
2025     <txbuf name="tile_7.ddm"/>\r
2026     <hw_channel name="tile_7.ahb0"/>\r
2027     <hw_channel name="tile_7.dnp"/>\r
2028     <hw_channel name="tile_3.dnp"/>\r
2029     <chbuf name="tile_3.dxm"/>\r
2030   </writepath>\r
2031 \r
2032   <writepath name="tile_7.ddmtodnp_4">\r
2033     <processor name="tile_7.magic"/>\r
2034     <txbuf name="tile_7.ddm"/>\r
2035     <hw_channel name="tile_7.ahb0"/>\r
2036     <hw_channel name="tile_7.dnp"/>\r
2037     <hw_channel name="tile_4.dnp"/>\r
2038     <chbuf name="tile_4.dxm"/>\r
2039   </writepath>\r
2040 \r
2041   <writepath name="tile_7.ddmtodnp_5">\r
2042     <processor name="tile_7.magic"/>\r
2043     <txbuf name="tile_7.ddm"/>\r
2044     <hw_channel name="tile_7.ahb0"/>\r
2045     <hw_channel name="tile_7.dnp"/>\r
2046     <hw_channel name="tile_5.dnp"/>\r
2047     <chbuf name="tile_5.dxm"/>\r
2048   </writepath>\r
2049 \r
2050   <writepath name="tile_7.ddmtodnp_6">\r
2051     <processor name="tile_7.magic"/>\r
2052     <txbuf name="tile_7.ddm"/>\r
2053     <hw_channel name="tile_7.ahb0"/>\r
2054     <hw_channel name="tile_7.dnp"/>\r
2055     <hw_channel name="tile_6.dnp"/>\r
2056     <chbuf name="tile_6.dxm"/>\r
2057   </writepath>\r
2058 \r
2059 </architecture>