1 #ifndef SCD_CONT_FSM_IF_H
2 #define SCD_CONT_FSM_IF_H
8 * Public interface for control manager state machines (master, slave, slave
14 virtual ~scd_cont_fsm_if() {}
17 * Signalize the FSM that the simulation is idle and the next event
18 * is in a specific amount of time (relative).
19 * \param time time of next event relative to current time
21 virtual void set_idle(const sc_core::sc_time& time) = 0;
24 * Signalizes the FSM that the simulation can be run.
26 virtual void set_busy() = 0;
29 * Signalizes the FSM that the simulation on this simulator has finished.
30 * No more events exist right now.
32 virtual void set_done() = 0;
35 * Signalizes the FSM that an error has occured and the simulation
36 * has to be brought down.
38 virtual void set_fail() = 0;
41 * Drives the control FSM. Shall be called repeatedly (i.e. from the
44 virtual void process() = 0;
47 * Indicates if the FSM is initiated and still working.
48 * \return true if the state is not init, terminated or failed
50 virtual bool active() const = 0;
53 * Indicates if another step should be simulated (i.e. the FSM is in
55 * \return true if the FSM is in busy state
57 virtual bool busy() const = 0;
60 * Indicates if the FSM is in the failed state.
61 * \return false if an error occured and the FSM stopped working
63 virtual bool failed() const = 0;
66 * Indicates if simulation time has to be advanced (i.e. the FSM
67 * is in the time state). If this is the case, the time step
68 * shall be obtained by calling get_time_step().
69 * \return true if the time has to be advanced
71 virtual bool advance_time() const = 0;
74 * Returns the time step by which the simulation time has to be advanced.
75 * Shall only be called in time state.
77 virtual const sc_core::sc_time& get_time_step() = 0;