4 #include "scd_simulator.h"
5 #include "scd_out_connector.h"
6 #include "scd_command_writer.h"
7 #include "scd_command_reader.h"
8 #include "fsm/scd_cont_state.h"
11 /* forward declaration */
12 class scd_cont_man_slave;
16 * Base class for all control slave states.
18 class scd_sts_base : public scd_cont_state
23 * \param sim the simulation environment
24 * \param fsm the FSM of this state
26 scd_sts_base(scd_simulator& sim, scd_cont_man_slave& fsm);
28 virtual ~scd_sts_base() {}
31 * Signalizes the state, that a failed message has been received
34 virtual void set_failed();
37 * Signalizes the state, that a time_req message has been received
40 virtual void recv_time_req();
43 * Signalizes the state, that a time_nack message has been received
46 virtual void recv_time_nack() {}
49 * Signalizes the state, that a time message has been received
52 virtual void recv_time(const sc_core::sc_time& time);
55 * Signalizes the state, that a term_req message has been received
58 virtual void recv_term_req();
61 * Signalizes the state, that a term_nack message has been received
64 virtual void recv_term_nack() {}
67 * Signalizes the state, that a term message has been received
70 virtual void recv_term();
74 void set_idle(const sc_core::sc_time& time) {}
81 bool advance_time() const;
82 const sc_core::sc_time& get_time_step();
85 scd_cont_man_slave& _fsm;
86 scd_command_writer& _writer;
87 scd_command_reader& _reader;
88 scd_out_connector& _connector;
89 scd_cont_state& _st_init;
90 scd_cont_state& _st_busy;
91 scd_cont_state& _st_idle;
92 scd_cont_state& _st_done;
93 scd_cont_state& _st_time_ack;
94 scd_cont_state& _st_time;
95 scd_cont_state& _st_term_ack;
96 scd_cont_state& _st_terminated;
97 scd_cont_state& _st_fail;
98 scd_cont_state& _st_failed;