+#ifndef SCD_CONT_FSM_IF_H
+#define SCD_CONT_FSM_IF_H
+
+#include "systemc"
+
+
+/**
+ * Public interface for control manager state machines (master, slave, slave
+ * wrapper).
+ */
+class scd_cont_fsm_if
+{
+public:
+ virtual ~scd_cont_fsm_if() {}
+
+ /**
+ * Signalize the FSM that the simulation is idle and the next event
+ * is in a specific amount of time (relative).
+ * \param time time of next event relative to current time
+ */
+ virtual void set_idle(const sc_core::sc_time& time) = 0;
+
+ /**
+ * Signalizes the FSM that the simulation can be run.
+ */
+ virtual void set_busy() = 0;
+
+ /**
+ * Signalizes the FSM that the simulation on this simulator has finished.
+ * No more events exist right now.
+ */
+ virtual void set_done() = 0;
+
+ /**
+ * Signalizes the FSM that an error has occured and the simulation
+ * has to be brought down.
+ */
+ virtual void set_fail() = 0;
+
+ /**
+ * Drives the control FSM. Shall be called repeatedly (i.e. from the
+ * main loop).
+ */
+ virtual void process() = 0;
+
+ /**
+ * Indicates if the FSM is initiated and still working.
+ * \return true if the state is not init, terminated or failed
+ */
+ virtual bool active() const = 0;
+
+ /**
+ * Indicates if another step should be simulated (i.e. the FSM is in
+ * the busy state).
+ * \return true if the FSM is in busy state
+ */
+ virtual bool busy() const = 0;
+
+ /**
+ * Indicates if the FSM is in the failed state.
+ * \return false if an error occured and the FSM stopped working
+ */
+ virtual bool failed() const = 0;
+
+ /**
+ * Indicates if simulation time has to be advanced (i.e. the FSM
+ * is in the time state). If this is the case, the time step
+ * shall be obtained by calling get_time_step().
+ * \return true if the time has to be advanced
+ */
+ virtual bool advance_time() const = 0;
+
+ /**
+ * Returns the time step by which the simulation time has to be advanced.
+ * Shall only be called in time state.
+ */
+ virtual const sc_core::sc_time& get_time_step() = 0;
+};
+
+#endif