dol: initial dol commit

[jump.git] / dol / examples / arch / rdt1.xml

diff --git a/dol/examples/arch/rdt1.xml b/dol/examples/arch/rdt1.xml
new file mode 100644 (file)
index 0000000..aa385c7
--- /dev/null
+++ b/dol/examples/arch/rdt1.xml
@@ -0,0 +1,139 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<architecture xmlns="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE"\r
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"\r
+  xsi:schemaLocation="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE\r
+                      http://www.tik.ee.ethz.ch/~shapes/schema/architecture.xsd"\r
+  name="RDT1">\r
+\r
+  <!-- rdt(tile_0) arm subsystem -->\r
+  <processor name="tile_0.arm" type="RISC">\r
+  </processor>\r
+\r
+  <memory name="tile_0.rdm" type="RAM">\r
+  </memory>\r
+\r
+  <hw_channel name="tile_0.armbus" type="BUS">\r
+    <configuration name="frequency" value="100000000"/>\r
+    <configuration name="bytespercycle" value="1"/>\r
+  </hw_channel>\r
+\r
+  <!-- rdt(tile_0) magic subsystem -->\r
+  <processor name="tile_0.magic" type="DSP">\r
+  </processor>\r
+\r
+  <memory name="tile_0.ddm" type="RAM">\r
+  </memory>\r
+\r
+  <hw_channel name="tile_0.magicbus" type="BUS">\r
+    <configuration name="frequency" value="100000000"/>\r
+    <configuration name="bytespercycle" value="1"/>\r
+  </hw_channel>\r
+\r
+  <hw_channel name="tile_0.dma" type="DMA">\r
+    <configuration name="frequency" value="100000000"/>\r
+    <configuration name="bytespercycle" value="1"/>\r
+  </hw_channel>\r
+\r
+  <!-- rdt(tile_0) distributed external memory -->\r
+  <memory name="tile_0.dxm" type="DXM">\r
+  </memory>\r
+\r
+  <!-- rdt(tile_0) ahb multi-layer bus -->\r
+  <hw_channel name="tile_0.ahb0" type="BUS">\r
+    <configuration name="frequency" value="100000000"/>\r
+    <configuration name="bytespercycle" value="1"/>\r
+  </hw_channel>\r
+\r
+  <hw_channel name="tile_0.ahb1" type="BUS">\r
+    <configuration name="frequency" value="100000000"/>\r
+    <configuration name="bytespercycle" value="1"/>\r
+  </hw_channel>\r
+\r
+  <!-- rdt(tile_0) dnp -->\r
+  <hw_channel name="tile_0.dnp" type="SPI">\r
+    <configuration name="frequency" value="100000000"/>\r
+    <configuration name="bytespercycle" value="1"/>\r
+  </hw_channel>\r
+\r
+  <!-- rdt(tile_0) on-tile communication paths -->\r
+  <!-- rdt(tile_0) arm paths via dxm-->\r
+  <writepath name="tile_0.rdmtodxm">\r
+    <processor name="tile_0.arm"/>\r
+    <txbuf name="tile_0.rdm"/>\r
+    <hw_channel name="tile_0.armbus"/>\r
+    <hw_channel name="tile_0.ahb1"/>\r
+    <chbuf name="tile_0.dxm"/>\r
+    <configuration name="delay" value="0"/>\r
+    <configuration name="cycles" value="8"/>\r
+  </writepath>\r
+\r
+  <readpath name="tile_0.rdmfromdxm">\r
+    <processor name="tile_0.arm"/>\r
+    <chbuf name="tile_0.dxm"/>\r
+    <hw_channel name="tile_0.ahb1"/>\r
+    <hw_channel name="tile_0.armbus"/>\r
+    <rxbuf name="tile_0.rdm"/>\r
+    <configuration name="delay" value="0"/>\r
+    <configuration name="cycles" value="8"/>\r
+  </readpath>\r
+\r
+  <!-- rdt(tile_0) arm paths via rdm-->\r
+  <writepath name="tile_0.rdmtordm">\r
+    <processor name="tile_0.arm"/>\r
+    <txbuf name="tile_0.rdm"/>\r
+    <hw_channel name="tile_0.armbus"/>\r
+    <chbuf name="tile_0.rdm"/>\r
+    <configuration name="delay" value="0"/>\r
+    <configuration name="cycles" value="8"/>\r
+  </writepath>\r
+\r
+  <readpath name="tile_0.rdmfromrdm">\r
+    <processor name="tile_0.arm"/>\r
+    <chbuf name="tile_0.rdm"/>\r
+    <hw_channel name="tile_0.armbus"/>\r
+    <rxbuf name="tile_0.rdm"/>\r
+    <configuration name="delay" value="0"/>\r
+    <configuration name="cycles" value="8"/>\r
+  </readpath>\r
+\r
+  <!-- rdt(tile_0) magic paths via ddm-->\r
+  <writepath name="tile_0.ddmtoddm">\r
+    <processor name="tile_0.magic"/>\r
+    <txbuf name="tile_0.ddm"/>\r
+    <hw_channel name="tile_0.magicbus"/>\r
+    <chbuf name="tile_0.ddm"/>\r
+    <configuration name="delay" value="0"/>\r
+    <configuration name="cycles" value="8"/>\r
+  </writepath>\r
+\r
+  <readpath name="tile_0.ddmfromddm">\r
+    <processor name="tile_0.magic"/>\r
+    <chbuf name="tile_0.ddm"/>\r
+    <hw_channel name="tile_0.magicbus"/>\r
+    <rxbuf name="tile_0.ddm"/>\r
+    <configuration name="delay" value="0"/>\r
+    <configuration name="cycles" value="8"/>\r
+  </readpath>\r
+\r
+  <!-- rdt(tile_0) magic paths via dxm-->\r
+  <writepath name="tile_0.ddmtodxm">\r
+    <processor name="tile_0.magic"/>\r
+    <txbuf name="tile_0.ddm"/>\r
+    <hw_channel name="tile_0.dma"/>\r
+    <hw_channel name="tile_0.ahb1"/>\r
+    <chbuf name="tile_0.dxm"/>\r
+    <configuration name="delay" value="0"/>\r
+    <configuration name="cycles" value="8"/>\r
+  </writepath>\r
+\r
+  <readpath name="tile_0.ddmfromdxm">\r
+    <processor name="tile_0.magic"/>\r
+    <chbuf name="tile_0.dxm"/>\r
+    <hw_channel name="tile_0.ahb1"/>\r
+    <hw_channel name="tile_0.dma"/>\r
+    <rxbuf name="tile_0.ddm"/>\r
+    <configuration name="delay" value="0"/>\r
+    <configuration name="cycles" value="8"/>\r
+  </readpath>\r
+\r
+</architecture>\r