--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<architecture xmlns="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE"\r
+ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"\r
+ xsi:schemaLocation="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE\r
+ http://www.tik.ee.ethz.ch/~shapes/schema/architecture.xsd"\r
+ name="RDT8">\r
+ <!-- 8 Tiles communicating via a mesh of DNPs -->\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_0 -->\r
+ <!--*****************************************************************-->\r
+ <processor name="tile_0.arm" type="RISC">\r
+ </processor>\r
+\r
+ <memory name="tile_0.rdm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_0.armbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <processor name="tile_0.magic" type="DSP">\r
+ </processor>\r
+\r
+ <memory name="tile_0.ddm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_0.magicbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_0.dma" type="DMA">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <memory name="tile_0.dxm" type="DXM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_0.ahb0" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_0.ahb1" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_0.dnp" type="SPI">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_1 -->\r
+ <!--*****************************************************************-->\r
+ <processor name="tile_1.arm" type="RISC">\r
+ </processor>\r
+\r
+ <memory name="tile_1.rdm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_1.armbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <processor name="tile_1.magic" type="DSP">\r
+ </processor>\r
+\r
+ <memory name="tile_1.ddm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_1.magicbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_1.dma" type="DMA">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <memory name="tile_1.dxm" type="DXM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_1.ahb0" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_1.ahb1" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_1.dnp" type="SPI">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_2 -->\r
+ <!--*****************************************************************-->\r
+ <processor name="tile_2.arm" type="RISC">\r
+ </processor>\r
+\r
+ <memory name="tile_2.rdm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_2.armbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <processor name="tile_2.magic" type="DSP">\r
+ </processor>\r
+\r
+ <memory name="tile_2.ddm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_2.magicbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_2.dma" type="DMA">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <memory name="tile_2.dxm" type="DXM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_2.ahb0" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_2.ahb1" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_2.dnp" type="SPI">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_3 -->\r
+ <!--*****************************************************************-->\r
+ <processor name="tile_3.arm" type="RISC">\r
+ </processor>\r
+\r
+ <memory name="tile_3.rdm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_3.armbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <processor name="tile_3.magic" type="DSP">\r
+ </processor>\r
+\r
+ <memory name="tile_3.ddm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_3.magicbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_3.dma" type="DMA">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <memory name="tile_3.dxm" type="DXM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_3.ahb0" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_3.ahb1" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_3.dnp" type="SPI">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_4 -->\r
+ <!--*****************************************************************-->\r
+ <processor name="tile_4.arm" type="RISC">\r
+ </processor>\r
+\r
+ <memory name="tile_4.rdm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_4.armbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <processor name="tile_4.magic" type="DSP">\r
+ </processor>\r
+\r
+ <memory name="tile_4.ddm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_4.magicbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_4.dma" type="DMA">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <memory name="tile_4.dxm" type="DXM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_4.ahb0" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_4.ahb1" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_4.dnp" type="SPI">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_5 -->\r
+ <!--*****************************************************************-->\r
+ <processor name="tile_5.arm" type="RISC">\r
+ </processor>\r
+\r
+ <memory name="tile_5.rdm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_5.armbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <processor name="tile_5.magic" type="DSP">\r
+ </processor>\r
+\r
+ <memory name="tile_5.ddm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_5.magicbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_5.dma" type="DMA">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <memory name="tile_5.dxm" type="DXM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_5.ahb0" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_5.ahb1" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_5.dnp" type="SPI">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_6 -->\r
+ <!--*****************************************************************-->\r
+ <processor name="tile_6.arm" type="RISC">\r
+ </processor>\r
+\r
+ <memory name="tile_6.rdm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_6.armbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <processor name="tile_6.magic" type="DSP">\r
+ </processor>\r
+\r
+ <memory name="tile_6.ddm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_6.magicbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_6.dma" type="DMA">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <memory name="tile_6.dxm" type="DXM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_6.ahb0" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_6.ahb1" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_6.dnp" type="SPI">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_7 -->\r
+ <!--*****************************************************************-->\r
+ <processor name="tile_7.arm" type="RISC">\r
+ </processor>\r
+\r
+ <memory name="tile_7.rdm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_7.armbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <processor name="tile_7.magic" type="DSP">\r
+ </processor>\r
+\r
+ <memory name="tile_7.ddm" type="RAM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_7.magicbus" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_7.dma" type="DMA">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <memory name="tile_7.dxm" type="DXM">\r
+ </memory>\r
+\r
+ <hw_channel name="tile_7.ahb0" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_7.ahb1" type="BUS">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+ <hw_channel name="tile_7.dnp" type="SPI">\r
+ <configuration name="frequency" value="100000000"/>\r
+ <configuration name="bytespercycle" value="1"/>\r
+ </hw_channel>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_0 communication paths -->\r
+ <!--*****************************************************************-->\r
+ <writepath name="tile_0.rdmtodxm">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.armbus"/>\r
+ <hw_channel name="tile_0.ahb1"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_0.rdmfromdxm">\r
+ <processor name="tile_0.arm"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ <hw_channel name="tile_0.ahb1"/>\r
+ <hw_channel name="tile_0.armbus"/>\r
+ <rxbuf name="tile_0.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_0.rdmtordm">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.armbus"/>\r
+ <chbuf name="tile_0.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_0.rdmfromrdm">\r
+ <processor name="tile_0.arm"/>\r
+ <chbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.armbus"/>\r
+ <rxbuf name="tile_0.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_0.ddmtoddm">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.magicbus"/>\r
+ <chbuf name="tile_0.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_0.ddmfromddm">\r
+ <processor name="tile_0.magic"/>\r
+ <chbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.magicbus"/>\r
+ <rxbuf name="tile_0.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_0.ddmtodxm">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.dma"/>\r
+ <hw_channel name="tile_0.ahb1"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_0.ddmfromdxm">\r
+ <processor name="tile_0.magic"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ <hw_channel name="tile_0.ahb1"/>\r
+ <hw_channel name="tile_0.dma"/>\r
+ <rxbuf name="tile_0.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <!-- tile_0 ARM inter-tile communication paths -->\r
+ <writepath name="tile_0.rdmtodnp_1">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.rdmtodnp_2">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.rdmtodnp_3">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.rdmtodnp_4">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.rdmtodnp_5">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.rdmtodnp_6">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.rdmtodnp_7">\r
+ <processor name="tile_0.arm"/>\r
+ <txbuf name="tile_0.rdm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+ <!-- tile_0 DSP inter-tile communication paths -->\r
+ <writepath name="tile_0.ddmtodnp_1">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.ddmtodnp_2">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.ddmtodnp_3">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.ddmtodnp_4">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.ddmtodnp_5">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.ddmtodnp_6">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_0.ddmtodnp_7">\r
+ <processor name="tile_0.magic"/>\r
+ <txbuf name="tile_0.ddm"/>\r
+ <hw_channel name="tile_0.ahb0"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_1 communication paths -->\r
+ <!--*****************************************************************-->\r
+ <writepath name="tile_1.rdmtodxm">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.armbus"/>\r
+ <hw_channel name="tile_1.ahb1"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_1.rdmfromdxm">\r
+ <processor name="tile_1.arm"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ <hw_channel name="tile_1.ahb1"/>\r
+ <hw_channel name="tile_1.armbus"/>\r
+ <rxbuf name="tile_1.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_1.rdmtordm">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.armbus"/>\r
+ <chbuf name="tile_1.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_1.rdmfromrdm">\r
+ <processor name="tile_1.arm"/>\r
+ <chbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.armbus"/>\r
+ <rxbuf name="tile_1.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_1.ddmtoddm">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.magicbus"/>\r
+ <chbuf name="tile_1.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_1.ddmfromddm">\r
+ <processor name="tile_1.magic"/>\r
+ <chbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.magicbus"/>\r
+ <rxbuf name="tile_1.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_1.ddmtodxm">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.dma"/>\r
+ <hw_channel name="tile_1.ahb1"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_1.ddmfromdxm">\r
+ <processor name="tile_1.magic"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ <hw_channel name="tile_1.ahb1"/>\r
+ <hw_channel name="tile_1.dma"/>\r
+ <rxbuf name="tile_1.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <!-- tile_1 ARM inter-tile communication paths -->\r
+ <writepath name="tile_1.rdmtodnp_0">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.rdmtodnp_2">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.rdmtodnp_3">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.rdmtodnp_4">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.rdmtodnp_5">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.rdmtodnp_6">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.rdmtodnp_7">\r
+ <processor name="tile_1.arm"/>\r
+ <txbuf name="tile_1.rdm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+ <!-- tile_1 DSP inter-tile communication paths -->\r
+ <writepath name="tile_1.ddmtodnp_0">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.ddmtodnp_2">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.ddmtodnp_3">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.ddmtodnp_4">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.ddmtodnp_5">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.ddmtodnp_6">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_1.ddmtodnp_7">\r
+ <processor name="tile_1.magic"/>\r
+ <txbuf name="tile_1.ddm"/>\r
+ <hw_channel name="tile_1.ahb0"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_2 communication paths -->\r
+ <!--*****************************************************************-->\r
+ <writepath name="tile_2.rdmtodxm">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.armbus"/>\r
+ <hw_channel name="tile_2.ahb1"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_2.rdmfromdxm">\r
+ <processor name="tile_2.arm"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ <hw_channel name="tile_2.ahb1"/>\r
+ <hw_channel name="tile_2.armbus"/>\r
+ <rxbuf name="tile_2.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_2.rdmtordm">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.armbus"/>\r
+ <chbuf name="tile_2.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_2.rdmfromrdm">\r
+ <processor name="tile_2.arm"/>\r
+ <chbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.armbus"/>\r
+ <rxbuf name="tile_2.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_2.ddmtoddm">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.magicbus"/>\r
+ <chbuf name="tile_2.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_2.ddmfromddm">\r
+ <processor name="tile_2.magic"/>\r
+ <chbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.magicbus"/>\r
+ <rxbuf name="tile_2.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_2.ddmtodxm">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.dma"/>\r
+ <hw_channel name="tile_2.ahb1"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_2.ddmfromdxm">\r
+ <processor name="tile_2.magic"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ <hw_channel name="tile_2.ahb1"/>\r
+ <hw_channel name="tile_2.dma"/>\r
+ <rxbuf name="tile_2.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <!-- tile_2 ARM inter-tile communication paths -->\r
+ <writepath name="tile_2.rdmtodnp_0">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.rdmtodnp_1">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.rdmtodnp_3">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.rdmtodnp_4">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.rdmtodnp_5">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.rdmtodnp_6">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.rdmtodnp_7">\r
+ <processor name="tile_2.arm"/>\r
+ <txbuf name="tile_2.rdm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+ <!-- tile_2 DSP inter-tile communication paths -->\r
+ <writepath name="tile_2.ddmtodnp_0">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.ddmtodnp_1">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.ddmtodnp_3">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.ddmtodnp_4">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.ddmtodnp_5">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.ddmtodnp_6">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_2.ddmtodnp_7">\r
+ <processor name="tile_2.magic"/>\r
+ <txbuf name="tile_2.ddm"/>\r
+ <hw_channel name="tile_2.ahb0"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_3 communication paths -->\r
+ <!--*****************************************************************-->\r
+ <writepath name="tile_3.rdmtodxm">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.armbus"/>\r
+ <hw_channel name="tile_3.ahb1"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_3.rdmfromdxm">\r
+ <processor name="tile_3.arm"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ <hw_channel name="tile_3.ahb1"/>\r
+ <hw_channel name="tile_3.armbus"/>\r
+ <rxbuf name="tile_3.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_3.rdmtordm">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.armbus"/>\r
+ <chbuf name="tile_3.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_3.rdmfromrdm">\r
+ <processor name="tile_3.arm"/>\r
+ <chbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.armbus"/>\r
+ <rxbuf name="tile_3.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_3.ddmtoddm">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.magicbus"/>\r
+ <chbuf name="tile_3.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_3.ddmfromddm">\r
+ <processor name="tile_3.magic"/>\r
+ <chbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.magicbus"/>\r
+ <rxbuf name="tile_3.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_3.ddmtodxm">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.dma"/>\r
+ <hw_channel name="tile_3.ahb1"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_3.ddmfromdxm">\r
+ <processor name="tile_3.magic"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ <hw_channel name="tile_3.ahb1"/>\r
+ <hw_channel name="tile_3.dma"/>\r
+ <rxbuf name="tile_3.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <!-- tile_3 ARM inter-tile communication paths -->\r
+ <writepath name="tile_3.rdmtodnp_0">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.rdmtodnp_1">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.rdmtodnp_2">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.rdmtodnp_4">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.rdmtodnp_5">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.rdmtodnp_6">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.rdmtodnp_7">\r
+ <processor name="tile_3.arm"/>\r
+ <txbuf name="tile_3.rdm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+ <!-- tile_3 DSP inter-tile communication paths -->\r
+ <writepath name="tile_3.ddmtodnp_0">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.ddmtodnp_1">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.ddmtodnp_2">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.ddmtodnp_4">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.ddmtodnp_5">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.ddmtodnp_6">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_3.ddmtodnp_7">\r
+ <processor name="tile_3.magic"/>\r
+ <txbuf name="tile_3.ddm"/>\r
+ <hw_channel name="tile_3.ahb0"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_4 communication paths -->\r
+ <!--*****************************************************************-->\r
+ <writepath name="tile_4.rdmtodxm">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.armbus"/>\r
+ <hw_channel name="tile_4.ahb1"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_4.rdmfromdxm">\r
+ <processor name="tile_4.arm"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ <hw_channel name="tile_4.ahb1"/>\r
+ <hw_channel name="tile_4.armbus"/>\r
+ <rxbuf name="tile_4.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_4.rdmtordm">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.armbus"/>\r
+ <chbuf name="tile_4.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_4.rdmfromrdm">\r
+ <processor name="tile_4.arm"/>\r
+ <chbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.armbus"/>\r
+ <rxbuf name="tile_4.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_4.ddmtoddm">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.magicbus"/>\r
+ <chbuf name="tile_4.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_4.ddmfromddm">\r
+ <processor name="tile_4.magic"/>\r
+ <chbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.magicbus"/>\r
+ <rxbuf name="tile_4.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_4.ddmtodxm">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.dma"/>\r
+ <hw_channel name="tile_4.ahb1"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_4.ddmfromdxm">\r
+ <processor name="tile_4.magic"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ <hw_channel name="tile_4.ahb1"/>\r
+ <hw_channel name="tile_4.dma"/>\r
+ <rxbuf name="tile_4.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <!-- tile_4 ARM inter-tile communication paths -->\r
+ <writepath name="tile_4.rdmtodnp_0">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.rdmtodnp_1">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.rdmtodnp_2">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.rdmtodnp_3">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.rdmtodnp_5">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.rdmtodnp_6">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.rdmtodnp_7">\r
+ <processor name="tile_4.arm"/>\r
+ <txbuf name="tile_4.rdm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+ <!-- tile_4 DSP inter-tile communication paths -->\r
+ <writepath name="tile_4.ddmtodnp_0">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.ddmtodnp_1">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.ddmtodnp_2">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.ddmtodnp_3">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.ddmtodnp_5">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.ddmtodnp_6">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_4.ddmtodnp_7">\r
+ <processor name="tile_4.magic"/>\r
+ <txbuf name="tile_4.ddm"/>\r
+ <hw_channel name="tile_4.ahb0"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_5 communication paths -->\r
+ <!--*****************************************************************-->\r
+ <writepath name="tile_5.rdmtodxm">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.armbus"/>\r
+ <hw_channel name="tile_5.ahb1"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_5.rdmfromdxm">\r
+ <processor name="tile_5.arm"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ <hw_channel name="tile_5.ahb1"/>\r
+ <hw_channel name="tile_5.armbus"/>\r
+ <rxbuf name="tile_5.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_5.rdmtordm">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.armbus"/>\r
+ <chbuf name="tile_5.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_5.rdmfromrdm">\r
+ <processor name="tile_5.arm"/>\r
+ <chbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.armbus"/>\r
+ <rxbuf name="tile_5.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_5.ddmtoddm">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.magicbus"/>\r
+ <chbuf name="tile_5.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_5.ddmfromddm">\r
+ <processor name="tile_5.magic"/>\r
+ <chbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.magicbus"/>\r
+ <rxbuf name="tile_5.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_5.ddmtodxm">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.dma"/>\r
+ <hw_channel name="tile_5.ahb1"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_5.ddmfromdxm">\r
+ <processor name="tile_5.magic"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ <hw_channel name="tile_5.ahb1"/>\r
+ <hw_channel name="tile_5.dma"/>\r
+ <rxbuf name="tile_5.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <!-- tile_5 ARM inter-tile communication paths -->\r
+ <writepath name="tile_5.rdmtodnp_0">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.rdmtodnp_1">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.rdmtodnp_2">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.rdmtodnp_3">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.rdmtodnp_4">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.rdmtodnp_6">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.rdmtodnp_7">\r
+ <processor name="tile_5.arm"/>\r
+ <txbuf name="tile_5.rdm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+ <!-- tile_5 DSP inter-tile communication paths -->\r
+ <writepath name="tile_5.ddmtodnp_0">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.ddmtodnp_1">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.ddmtodnp_2">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.ddmtodnp_3">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.ddmtodnp_4">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.ddmtodnp_6">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_5.ddmtodnp_7">\r
+ <processor name="tile_5.magic"/>\r
+ <txbuf name="tile_5.ddm"/>\r
+ <hw_channel name="tile_5.ahb0"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_6 communication paths -->\r
+ <!--*****************************************************************-->\r
+ <writepath name="tile_6.rdmtodxm">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.armbus"/>\r
+ <hw_channel name="tile_6.ahb1"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_6.rdmfromdxm">\r
+ <processor name="tile_6.arm"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ <hw_channel name="tile_6.ahb1"/>\r
+ <hw_channel name="tile_6.armbus"/>\r
+ <rxbuf name="tile_6.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_6.rdmtordm">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.armbus"/>\r
+ <chbuf name="tile_6.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_6.rdmfromrdm">\r
+ <processor name="tile_6.arm"/>\r
+ <chbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.armbus"/>\r
+ <rxbuf name="tile_6.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_6.ddmtoddm">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.magicbus"/>\r
+ <chbuf name="tile_6.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_6.ddmfromddm">\r
+ <processor name="tile_6.magic"/>\r
+ <chbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.magicbus"/>\r
+ <rxbuf name="tile_6.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_6.ddmtodxm">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.dma"/>\r
+ <hw_channel name="tile_6.ahb1"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_6.ddmfromdxm">\r
+ <processor name="tile_6.magic"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ <hw_channel name="tile_6.ahb1"/>\r
+ <hw_channel name="tile_6.dma"/>\r
+ <rxbuf name="tile_6.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <!-- tile_6 ARM inter-tile communication paths -->\r
+ <writepath name="tile_6.rdmtodnp_0">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.rdmtodnp_1">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.rdmtodnp_2">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.rdmtodnp_3">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.rdmtodnp_4">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.rdmtodnp_5">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.rdmtodnp_7">\r
+ <processor name="tile_6.arm"/>\r
+ <txbuf name="tile_6.rdm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+ <!-- tile_6 DSP inter-tile communication paths -->\r
+ <writepath name="tile_6.ddmtodnp_0">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.ddmtodnp_1">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.ddmtodnp_2">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.ddmtodnp_3">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.ddmtodnp_4">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.ddmtodnp_5">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_6.ddmtodnp_7">\r
+ <processor name="tile_6.magic"/>\r
+ <txbuf name="tile_6.ddm"/>\r
+ <hw_channel name="tile_6.ahb0"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ </writepath>\r
+\r
+\r
+ <!--*****************************************************************-->\r
+ <!-- tile_7 communication paths -->\r
+ <!--*****************************************************************-->\r
+ <writepath name="tile_7.rdmtodxm">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.armbus"/>\r
+ <hw_channel name="tile_7.ahb1"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_7.rdmfromdxm">\r
+ <processor name="tile_7.arm"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ <hw_channel name="tile_7.ahb1"/>\r
+ <hw_channel name="tile_7.armbus"/>\r
+ <rxbuf name="tile_7.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_7.rdmtordm">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.armbus"/>\r
+ <chbuf name="tile_7.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_7.rdmfromrdm">\r
+ <processor name="tile_7.arm"/>\r
+ <chbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.armbus"/>\r
+ <rxbuf name="tile_7.rdm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_7.ddmtoddm">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.magicbus"/>\r
+ <chbuf name="tile_7.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_7.ddmfromddm">\r
+ <processor name="tile_7.magic"/>\r
+ <chbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.magicbus"/>\r
+ <rxbuf name="tile_7.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <writepath name="tile_7.ddmtodxm">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.dma"/>\r
+ <hw_channel name="tile_7.ahb1"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </writepath>\r
+\r
+ <readpath name="tile_7.ddmfromdxm">\r
+ <processor name="tile_7.magic"/>\r
+ <chbuf name="tile_7.dxm"/>\r
+ <hw_channel name="tile_7.ahb1"/>\r
+ <hw_channel name="tile_7.dma"/>\r
+ <rxbuf name="tile_7.ddm"/>\r
+ <configuration name="delay" value="0"/>\r
+ <configuration name="cycles" value="8"/>\r
+ </readpath>\r
+\r
+ <!-- tile_7 ARM inter-tile communication paths -->\r
+ <writepath name="tile_7.rdmtodnp_0">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.rdmtodnp_1">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.rdmtodnp_2">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.rdmtodnp_3">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.rdmtodnp_4">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.rdmtodnp_5">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.rdmtodnp_6">\r
+ <processor name="tile_7.arm"/>\r
+ <txbuf name="tile_7.rdm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+ <!-- tile_7 DSP inter-tile communication paths -->\r
+ <writepath name="tile_7.ddmtodnp_0">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_0.dnp"/>\r
+ <chbuf name="tile_0.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.ddmtodnp_1">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_1.dnp"/>\r
+ <chbuf name="tile_1.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.ddmtodnp_2">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_2.dnp"/>\r
+ <chbuf name="tile_2.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.ddmtodnp_3">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_3.dnp"/>\r
+ <chbuf name="tile_3.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.ddmtodnp_4">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_4.dnp"/>\r
+ <chbuf name="tile_4.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.ddmtodnp_5">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_5.dnp"/>\r
+ <chbuf name="tile_5.dxm"/>\r
+ </writepath>\r
+\r
+ <writepath name="tile_7.ddmtodnp_6">\r
+ <processor name="tile_7.magic"/>\r
+ <txbuf name="tile_7.ddm"/>\r
+ <hw_channel name="tile_7.ahb0"/>\r
+ <hw_channel name="tile_7.dnp"/>\r
+ <hw_channel name="tile_6.dnp"/>\r
+ <chbuf name="tile_6.dxm"/>\r
+ </writepath>\r
+\r
+</architecture>
\ No newline at end of file
projects / jump.git / blobdiff