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diff --git a/dol/examples/arch/rdt1.xml b/dol/examples/arch/rdt1.xml
new file mode 100644
index 0000000..aa385c7
--- /dev/null
+++ b/dol/examples/arch/rdt1.xml
@@ -0,0 +1,139 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<architecture xmlns="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE"
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:schemaLocation="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE
+                      http://www.tik.ee.ethz.ch/~shapes/schema/architecture.xsd"
+  name="RDT1">
+
+  <!-- rdt(tile_0) arm subsystem -->
+  <processor name="tile_0.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_0.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_0.armbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!-- rdt(tile_0) magic subsystem -->
+  <processor name="tile_0.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_0.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_0.magicbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_0.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!-- rdt(tile_0) distributed external memory -->
+  <memory name="tile_0.dxm" type="DXM">
+  </memory>
+
+  <!-- rdt(tile_0) ahb multi-layer bus -->
+  <hw_channel name="tile_0.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_0.ahb1" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!-- rdt(tile_0) dnp -->
+  <hw_channel name="tile_0.dnp" type="SPI">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!-- rdt(tile_0) on-tile communication paths -->
+  <!-- rdt(tile_0) arm paths via dxm-->
+  <writepath name="tile_0.rdmtodxm">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.armbus"/>
+    <hw_channel name="tile_0.ahb1"/>
+    <chbuf name="tile_0.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_0.rdmfromdxm">
+    <processor name="tile_0.arm"/>
+    <chbuf name="tile_0.dxm"/>
+    <hw_channel name="tile_0.ahb1"/>
+    <hw_channel name="tile_0.armbus"/>
+    <rxbuf name="tile_0.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- rdt(tile_0) arm paths via rdm-->
+  <writepath name="tile_0.rdmtordm">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.armbus"/>
+    <chbuf name="tile_0.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_0.rdmfromrdm">
+    <processor name="tile_0.arm"/>
+    <chbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.armbus"/>
+    <rxbuf name="tile_0.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- rdt(tile_0) magic paths via ddm-->
+  <writepath name="tile_0.ddmtoddm">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.magicbus"/>
+    <chbuf name="tile_0.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_0.ddmfromddm">
+    <processor name="tile_0.magic"/>
+    <chbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.magicbus"/>
+    <rxbuf name="tile_0.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- rdt(tile_0) magic paths via dxm-->
+  <writepath name="tile_0.ddmtodxm">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.dma"/>
+    <hw_channel name="tile_0.ahb1"/>
+    <chbuf name="tile_0.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_0.ddmfromdxm">
+    <processor name="tile_0.magic"/>
+    <chbuf name="tile_0.dxm"/>
+    <hw_channel name="tile_0.ahb1"/>
+    <hw_channel name="tile_0.dma"/>
+    <rxbuf name="tile_0.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+</architecture>