X-Git-Url: http://sraa.de/git/?a=blobdiff_plain;f=dol%2Fexamples%2Farch%2Frdt8.xml;fp=dol%2Fexamples%2Farch%2Frdt8.xml;h=5f7189bcdd197bd43d3636392e1e80af1b4453ce;hb=8c411cf24ed0eb889191aaeafd8fa1e69081df42;hp=0000000000000000000000000000000000000000;hpb=dea7a4fb1ed110d3ce6e6d9255103d724bd66c0e;p=jump.git

diff --git a/dol/examples/arch/rdt8.xml b/dol/examples/arch/rdt8.xml
new file mode 100644
index 0000000..5f7189b
--- /dev/null
+++ b/dol/examples/arch/rdt8.xml
@@ -0,0 +1,2059 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<architecture xmlns="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE"
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:schemaLocation="http://www.tik.ee.ethz.ch/~shapes/schema/ARCHITECTURE
+                      http://www.tik.ee.ethz.ch/~shapes/schema/architecture.xsd"
+  name="RDT8">
+  <!-- 8 Tiles communicating via a mesh of DNPs -->
+
+  <!--*****************************************************************-->
+  <!-- tile_0 -->
+  <!--*****************************************************************-->
+  <processor name="tile_0.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_0.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_0.armbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <processor name="tile_0.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_0.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_0.magicbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_0.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <memory name="tile_0.dxm" type="DXM">
+  </memory>
+
+  <hw_channel name="tile_0.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_0.ahb1" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_0.dnp" type="SPI">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!--*****************************************************************-->
+  <!-- tile_1 -->
+  <!--*****************************************************************-->
+  <processor name="tile_1.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_1.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_1.armbus" type="BUS">
+   <configuration name="frequency" value="100000000"/>
+   <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <processor name="tile_1.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_1.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_1.magicbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_1.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <memory name="tile_1.dxm" type="DXM">
+  </memory>
+
+  <hw_channel name="tile_1.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_1.ahb1" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_1.dnp" type="SPI">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!--*****************************************************************-->
+  <!-- tile_2 -->
+  <!--*****************************************************************-->
+  <processor name="tile_2.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_2.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_2.armbus" type="BUS">
+   <configuration name="frequency" value="100000000"/>
+   <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <processor name="tile_2.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_2.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_2.magicbus" type="BUS">
+   <configuration name="frequency" value="100000000"/>
+   <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_2.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <memory name="tile_2.dxm" type="DXM">
+  </memory>
+
+  <hw_channel name="tile_2.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_2.ahb1" type="BUS">
+   <configuration name="frequency" value="100000000"/>
+   <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_2.dnp" type="SPI">
+   <configuration name="frequency" value="100000000"/>
+   <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!--*****************************************************************-->
+  <!-- tile_3 -->
+  <!--*****************************************************************-->
+  <processor name="tile_3.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_3.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_3.armbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <processor name="tile_3.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_3.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_3.magicbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_3.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <memory name="tile_3.dxm" type="DXM">
+  </memory>
+
+  <hw_channel name="tile_3.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_3.ahb1" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_3.dnp" type="SPI">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!--*****************************************************************-->
+  <!-- tile_4 -->
+  <!--*****************************************************************-->
+  <processor name="tile_4.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_4.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_4.armbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <processor name="tile_4.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_4.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_4.magicbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_4.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <memory name="tile_4.dxm" type="DXM">
+  </memory>
+
+  <hw_channel name="tile_4.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_4.ahb1" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_4.dnp" type="SPI">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_5 -->
+  <!--*****************************************************************-->
+  <processor name="tile_5.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_5.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_5.armbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <processor name="tile_5.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_5.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_5.magicbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_5.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <memory name="tile_5.dxm" type="DXM">
+  </memory>
+
+  <hw_channel name="tile_5.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_5.ahb1" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_5.dnp" type="SPI">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <!--*****************************************************************-->
+  <!-- tile_6 -->
+  <!--*****************************************************************-->
+  <processor name="tile_6.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_6.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_6.armbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <processor name="tile_6.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_6.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_6.magicbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_6.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <memory name="tile_6.dxm" type="DXM">
+  </memory>
+
+  <hw_channel name="tile_6.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_6.ahb1" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_6.dnp" type="SPI">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_7 -->
+  <!--*****************************************************************-->
+  <processor name="tile_7.arm" type="RISC">
+  </processor>
+
+  <memory name="tile_7.rdm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_7.armbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <processor name="tile_7.magic" type="DSP">
+  </processor>
+
+  <memory name="tile_7.ddm" type="RAM">
+  </memory>
+
+  <hw_channel name="tile_7.magicbus" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_7.dma" type="DMA">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <memory name="tile_7.dxm" type="DXM">
+  </memory>
+
+  <hw_channel name="tile_7.ahb0" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_7.ahb1" type="BUS">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+  <hw_channel name="tile_7.dnp" type="SPI">
+    <configuration name="frequency" value="100000000"/>
+    <configuration name="bytespercycle" value="1"/>
+  </hw_channel>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_0 communication paths -->
+  <!--*****************************************************************-->
+  <writepath name="tile_0.rdmtodxm">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.armbus"/>
+    <hw_channel name="tile_0.ahb1"/>
+    <chbuf name="tile_0.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_0.rdmfromdxm">
+    <processor name="tile_0.arm"/>
+    <chbuf name="tile_0.dxm"/>
+    <hw_channel name="tile_0.ahb1"/>
+    <hw_channel name="tile_0.armbus"/>
+    <rxbuf name="tile_0.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_0.rdmtordm">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.armbus"/>
+    <chbuf name="tile_0.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_0.rdmfromrdm">
+    <processor name="tile_0.arm"/>
+    <chbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.armbus"/>
+    <rxbuf name="tile_0.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_0.ddmtoddm">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.magicbus"/>
+    <chbuf name="tile_0.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_0.ddmfromddm">
+    <processor name="tile_0.magic"/>
+    <chbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.magicbus"/>
+    <rxbuf name="tile_0.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_0.ddmtodxm">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.dma"/>
+    <hw_channel name="tile_0.ahb1"/>
+    <chbuf name="tile_0.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_0.ddmfromdxm">
+    <processor name="tile_0.magic"/>
+    <chbuf name="tile_0.dxm"/>
+    <hw_channel name="tile_0.ahb1"/>
+    <hw_channel name="tile_0.dma"/>
+    <rxbuf name="tile_0.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- tile_0 ARM inter-tile communication paths -->
+  <writepath name="tile_0.rdmtodnp_1">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.rdmtodnp_2">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.rdmtodnp_3">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.rdmtodnp_4">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.rdmtodnp_5">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.rdmtodnp_6">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.rdmtodnp_7">
+    <processor name="tile_0.arm"/>
+    <txbuf name="tile_0.rdm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+  <!-- tile_0 DSP inter-tile communication paths -->
+  <writepath name="tile_0.ddmtodnp_1">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.ddmtodnp_2">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.ddmtodnp_3">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.ddmtodnp_4">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.ddmtodnp_5">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.ddmtodnp_6">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_0.ddmtodnp_7">
+    <processor name="tile_0.magic"/>
+    <txbuf name="tile_0.ddm"/>
+    <hw_channel name="tile_0.ahb0"/>
+    <hw_channel name="tile_0.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_1 communication paths -->
+  <!--*****************************************************************-->
+  <writepath name="tile_1.rdmtodxm">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.armbus"/>
+    <hw_channel name="tile_1.ahb1"/>
+    <chbuf name="tile_1.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_1.rdmfromdxm">
+    <processor name="tile_1.arm"/>
+    <chbuf name="tile_1.dxm"/>
+    <hw_channel name="tile_1.ahb1"/>
+    <hw_channel name="tile_1.armbus"/>
+    <rxbuf name="tile_1.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_1.rdmtordm">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.armbus"/>
+    <chbuf name="tile_1.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_1.rdmfromrdm">
+    <processor name="tile_1.arm"/>
+    <chbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.armbus"/>
+    <rxbuf name="tile_1.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_1.ddmtoddm">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.magicbus"/>
+    <chbuf name="tile_1.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_1.ddmfromddm">
+    <processor name="tile_1.magic"/>
+    <chbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.magicbus"/>
+    <rxbuf name="tile_1.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_1.ddmtodxm">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.dma"/>
+    <hw_channel name="tile_1.ahb1"/>
+    <chbuf name="tile_1.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_1.ddmfromdxm">
+    <processor name="tile_1.magic"/>
+    <chbuf name="tile_1.dxm"/>
+    <hw_channel name="tile_1.ahb1"/>
+    <hw_channel name="tile_1.dma"/>
+    <rxbuf name="tile_1.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- tile_1 ARM inter-tile communication paths -->
+  <writepath name="tile_1.rdmtodnp_0">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.rdmtodnp_2">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.rdmtodnp_3">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.rdmtodnp_4">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.rdmtodnp_5">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.rdmtodnp_6">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.rdmtodnp_7">
+    <processor name="tile_1.arm"/>
+    <txbuf name="tile_1.rdm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+  <!-- tile_1 DSP inter-tile communication paths -->
+  <writepath name="tile_1.ddmtodnp_0">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.ddmtodnp_2">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.ddmtodnp_3">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.ddmtodnp_4">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.ddmtodnp_5">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.ddmtodnp_6">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_1.ddmtodnp_7">
+    <processor name="tile_1.magic"/>
+    <txbuf name="tile_1.ddm"/>
+    <hw_channel name="tile_1.ahb0"/>
+    <hw_channel name="tile_1.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_2 communication paths -->
+  <!--*****************************************************************-->
+  <writepath name="tile_2.rdmtodxm">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.armbus"/>
+    <hw_channel name="tile_2.ahb1"/>
+    <chbuf name="tile_2.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_2.rdmfromdxm">
+    <processor name="tile_2.arm"/>
+    <chbuf name="tile_2.dxm"/>
+    <hw_channel name="tile_2.ahb1"/>
+    <hw_channel name="tile_2.armbus"/>
+    <rxbuf name="tile_2.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_2.rdmtordm">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.armbus"/>
+    <chbuf name="tile_2.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_2.rdmfromrdm">
+    <processor name="tile_2.arm"/>
+    <chbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.armbus"/>
+    <rxbuf name="tile_2.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_2.ddmtoddm">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.magicbus"/>
+    <chbuf name="tile_2.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_2.ddmfromddm">
+    <processor name="tile_2.magic"/>
+    <chbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.magicbus"/>
+    <rxbuf name="tile_2.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_2.ddmtodxm">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.dma"/>
+    <hw_channel name="tile_2.ahb1"/>
+    <chbuf name="tile_2.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_2.ddmfromdxm">
+    <processor name="tile_2.magic"/>
+    <chbuf name="tile_2.dxm"/>
+    <hw_channel name="tile_2.ahb1"/>
+    <hw_channel name="tile_2.dma"/>
+    <rxbuf name="tile_2.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- tile_2 ARM inter-tile communication paths -->
+  <writepath name="tile_2.rdmtodnp_0">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.rdmtodnp_1">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.rdmtodnp_3">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.rdmtodnp_4">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.rdmtodnp_5">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.rdmtodnp_6">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.rdmtodnp_7">
+    <processor name="tile_2.arm"/>
+    <txbuf name="tile_2.rdm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+  <!-- tile_2 DSP inter-tile communication paths -->
+  <writepath name="tile_2.ddmtodnp_0">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.ddmtodnp_1">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.ddmtodnp_3">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.ddmtodnp_4">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.ddmtodnp_5">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.ddmtodnp_6">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_2.ddmtodnp_7">
+    <processor name="tile_2.magic"/>
+    <txbuf name="tile_2.ddm"/>
+    <hw_channel name="tile_2.ahb0"/>
+    <hw_channel name="tile_2.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_3 communication paths -->
+  <!--*****************************************************************-->
+  <writepath name="tile_3.rdmtodxm">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.armbus"/>
+    <hw_channel name="tile_3.ahb1"/>
+    <chbuf name="tile_3.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_3.rdmfromdxm">
+    <processor name="tile_3.arm"/>
+    <chbuf name="tile_3.dxm"/>
+    <hw_channel name="tile_3.ahb1"/>
+    <hw_channel name="tile_3.armbus"/>
+    <rxbuf name="tile_3.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_3.rdmtordm">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.armbus"/>
+    <chbuf name="tile_3.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_3.rdmfromrdm">
+    <processor name="tile_3.arm"/>
+    <chbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.armbus"/>
+    <rxbuf name="tile_3.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_3.ddmtoddm">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.magicbus"/>
+    <chbuf name="tile_3.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_3.ddmfromddm">
+    <processor name="tile_3.magic"/>
+    <chbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.magicbus"/>
+    <rxbuf name="tile_3.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_3.ddmtodxm">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.dma"/>
+    <hw_channel name="tile_3.ahb1"/>
+    <chbuf name="tile_3.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_3.ddmfromdxm">
+    <processor name="tile_3.magic"/>
+    <chbuf name="tile_3.dxm"/>
+    <hw_channel name="tile_3.ahb1"/>
+    <hw_channel name="tile_3.dma"/>
+    <rxbuf name="tile_3.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- tile_3 ARM inter-tile communication paths -->
+  <writepath name="tile_3.rdmtodnp_0">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.rdmtodnp_1">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.rdmtodnp_2">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.rdmtodnp_4">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.rdmtodnp_5">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.rdmtodnp_6">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.rdmtodnp_7">
+    <processor name="tile_3.arm"/>
+    <txbuf name="tile_3.rdm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+  <!-- tile_3 DSP inter-tile communication paths -->
+  <writepath name="tile_3.ddmtodnp_0">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.ddmtodnp_1">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.ddmtodnp_2">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.ddmtodnp_4">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.ddmtodnp_5">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.ddmtodnp_6">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_3.ddmtodnp_7">
+    <processor name="tile_3.magic"/>
+    <txbuf name="tile_3.ddm"/>
+    <hw_channel name="tile_3.ahb0"/>
+    <hw_channel name="tile_3.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_4 communication paths -->
+  <!--*****************************************************************-->
+  <writepath name="tile_4.rdmtodxm">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.armbus"/>
+    <hw_channel name="tile_4.ahb1"/>
+    <chbuf name="tile_4.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_4.rdmfromdxm">
+    <processor name="tile_4.arm"/>
+    <chbuf name="tile_4.dxm"/>
+    <hw_channel name="tile_4.ahb1"/>
+    <hw_channel name="tile_4.armbus"/>
+    <rxbuf name="tile_4.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_4.rdmtordm">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.armbus"/>
+    <chbuf name="tile_4.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_4.rdmfromrdm">
+    <processor name="tile_4.arm"/>
+    <chbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.armbus"/>
+    <rxbuf name="tile_4.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_4.ddmtoddm">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.magicbus"/>
+    <chbuf name="tile_4.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_4.ddmfromddm">
+    <processor name="tile_4.magic"/>
+    <chbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.magicbus"/>
+    <rxbuf name="tile_4.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_4.ddmtodxm">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.dma"/>
+    <hw_channel name="tile_4.ahb1"/>
+    <chbuf name="tile_4.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_4.ddmfromdxm">
+    <processor name="tile_4.magic"/>
+    <chbuf name="tile_4.dxm"/>
+    <hw_channel name="tile_4.ahb1"/>
+    <hw_channel name="tile_4.dma"/>
+    <rxbuf name="tile_4.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- tile_4 ARM inter-tile communication paths -->
+  <writepath name="tile_4.rdmtodnp_0">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.rdmtodnp_1">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.rdmtodnp_2">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.rdmtodnp_3">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.rdmtodnp_5">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.rdmtodnp_6">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.rdmtodnp_7">
+    <processor name="tile_4.arm"/>
+    <txbuf name="tile_4.rdm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+  <!-- tile_4 DSP inter-tile communication paths -->
+  <writepath name="tile_4.ddmtodnp_0">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.ddmtodnp_1">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.ddmtodnp_2">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.ddmtodnp_3">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.ddmtodnp_5">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.ddmtodnp_6">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_4.ddmtodnp_7">
+    <processor name="tile_4.magic"/>
+    <txbuf name="tile_4.ddm"/>
+    <hw_channel name="tile_4.ahb0"/>
+    <hw_channel name="tile_4.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_5 communication paths -->
+  <!--*****************************************************************-->
+  <writepath name="tile_5.rdmtodxm">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.armbus"/>
+    <hw_channel name="tile_5.ahb1"/>
+    <chbuf name="tile_5.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_5.rdmfromdxm">
+    <processor name="tile_5.arm"/>
+    <chbuf name="tile_5.dxm"/>
+    <hw_channel name="tile_5.ahb1"/>
+    <hw_channel name="tile_5.armbus"/>
+    <rxbuf name="tile_5.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_5.rdmtordm">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.armbus"/>
+    <chbuf name="tile_5.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_5.rdmfromrdm">
+    <processor name="tile_5.arm"/>
+    <chbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.armbus"/>
+    <rxbuf name="tile_5.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_5.ddmtoddm">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.magicbus"/>
+    <chbuf name="tile_5.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_5.ddmfromddm">
+    <processor name="tile_5.magic"/>
+    <chbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.magicbus"/>
+    <rxbuf name="tile_5.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_5.ddmtodxm">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.dma"/>
+    <hw_channel name="tile_5.ahb1"/>
+    <chbuf name="tile_5.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_5.ddmfromdxm">
+    <processor name="tile_5.magic"/>
+    <chbuf name="tile_5.dxm"/>
+    <hw_channel name="tile_5.ahb1"/>
+    <hw_channel name="tile_5.dma"/>
+    <rxbuf name="tile_5.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- tile_5 ARM inter-tile communication paths -->
+  <writepath name="tile_5.rdmtodnp_0">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.rdmtodnp_1">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.rdmtodnp_2">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.rdmtodnp_3">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.rdmtodnp_4">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.rdmtodnp_6">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.rdmtodnp_7">
+    <processor name="tile_5.arm"/>
+    <txbuf name="tile_5.rdm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+  <!-- tile_5 DSP inter-tile communication paths -->
+  <writepath name="tile_5.ddmtodnp_0">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.ddmtodnp_1">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.ddmtodnp_2">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.ddmtodnp_3">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.ddmtodnp_4">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.ddmtodnp_6">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <writepath name="tile_5.ddmtodnp_7">
+    <processor name="tile_5.magic"/>
+    <txbuf name="tile_5.ddm"/>
+    <hw_channel name="tile_5.ahb0"/>
+    <hw_channel name="tile_5.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_6 communication paths -->
+  <!--*****************************************************************-->
+  <writepath name="tile_6.rdmtodxm">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.armbus"/>
+    <hw_channel name="tile_6.ahb1"/>
+    <chbuf name="tile_6.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_6.rdmfromdxm">
+    <processor name="tile_6.arm"/>
+    <chbuf name="tile_6.dxm"/>
+    <hw_channel name="tile_6.ahb1"/>
+    <hw_channel name="tile_6.armbus"/>
+    <rxbuf name="tile_6.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_6.rdmtordm">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.armbus"/>
+    <chbuf name="tile_6.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_6.rdmfromrdm">
+    <processor name="tile_6.arm"/>
+    <chbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.armbus"/>
+    <rxbuf name="tile_6.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_6.ddmtoddm">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.magicbus"/>
+    <chbuf name="tile_6.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_6.ddmfromddm">
+    <processor name="tile_6.magic"/>
+    <chbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.magicbus"/>
+    <rxbuf name="tile_6.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_6.ddmtodxm">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.dma"/>
+    <hw_channel name="tile_6.ahb1"/>
+    <chbuf name="tile_6.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_6.ddmfromdxm">
+    <processor name="tile_6.magic"/>
+    <chbuf name="tile_6.dxm"/>
+    <hw_channel name="tile_6.ahb1"/>
+    <hw_channel name="tile_6.dma"/>
+    <rxbuf name="tile_6.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- tile_6 ARM inter-tile communication paths -->
+  <writepath name="tile_6.rdmtodnp_0">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.rdmtodnp_1">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.rdmtodnp_2">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.rdmtodnp_3">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.rdmtodnp_4">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.rdmtodnp_5">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.rdmtodnp_7">
+    <processor name="tile_6.arm"/>
+    <txbuf name="tile_6.rdm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+  <!-- tile_6 DSP inter-tile communication paths -->
+  <writepath name="tile_6.ddmtodnp_0">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.ddmtodnp_1">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.ddmtodnp_2">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.ddmtodnp_3">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.ddmtodnp_4">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.ddmtodnp_5">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_6.ddmtodnp_7">
+    <processor name="tile_6.magic"/>
+    <txbuf name="tile_6.ddm"/>
+    <hw_channel name="tile_6.ahb0"/>
+    <hw_channel name="tile_6.dnp"/>
+    <hw_channel name="tile_7.dnp"/>
+    <chbuf name="tile_7.dxm"/>
+  </writepath>
+
+
+  <!--*****************************************************************-->
+  <!-- tile_7 communication paths -->
+  <!--*****************************************************************-->
+  <writepath name="tile_7.rdmtodxm">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.armbus"/>
+    <hw_channel name="tile_7.ahb1"/>
+    <chbuf name="tile_7.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_7.rdmfromdxm">
+    <processor name="tile_7.arm"/>
+    <chbuf name="tile_7.dxm"/>
+    <hw_channel name="tile_7.ahb1"/>
+    <hw_channel name="tile_7.armbus"/>
+    <rxbuf name="tile_7.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_7.rdmtordm">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.armbus"/>
+    <chbuf name="tile_7.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_7.rdmfromrdm">
+    <processor name="tile_7.arm"/>
+    <chbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.armbus"/>
+    <rxbuf name="tile_7.rdm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_7.ddmtoddm">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.magicbus"/>
+    <chbuf name="tile_7.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_7.ddmfromddm">
+    <processor name="tile_7.magic"/>
+    <chbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.magicbus"/>
+    <rxbuf name="tile_7.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <writepath name="tile_7.ddmtodxm">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.dma"/>
+    <hw_channel name="tile_7.ahb1"/>
+    <chbuf name="tile_7.dxm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </writepath>
+
+  <readpath name="tile_7.ddmfromdxm">
+    <processor name="tile_7.magic"/>
+    <chbuf name="tile_7.dxm"/>
+    <hw_channel name="tile_7.ahb1"/>
+    <hw_channel name="tile_7.dma"/>
+    <rxbuf name="tile_7.ddm"/>
+    <configuration name="delay" value="0"/>
+    <configuration name="cycles" value="8"/>
+  </readpath>
+
+  <!-- tile_7 ARM inter-tile communication paths -->
+  <writepath name="tile_7.rdmtodnp_0">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.rdmtodnp_1">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.rdmtodnp_2">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.rdmtodnp_3">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.rdmtodnp_4">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.rdmtodnp_5">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.rdmtodnp_6">
+    <processor name="tile_7.arm"/>
+    <txbuf name="tile_7.rdm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+  <!-- tile_7 DSP inter-tile communication paths -->
+  <writepath name="tile_7.ddmtodnp_0">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_0.dnp"/>
+    <chbuf name="tile_0.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.ddmtodnp_1">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_1.dnp"/>
+    <chbuf name="tile_1.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.ddmtodnp_2">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_2.dnp"/>
+    <chbuf name="tile_2.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.ddmtodnp_3">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_3.dnp"/>
+    <chbuf name="tile_3.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.ddmtodnp_4">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_4.dnp"/>
+    <chbuf name="tile_4.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.ddmtodnp_5">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_5.dnp"/>
+    <chbuf name="tile_5.dxm"/>
+  </writepath>
+
+  <writepath name="tile_7.ddmtodnp_6">
+    <processor name="tile_7.magic"/>
+    <txbuf name="tile_7.ddm"/>
+    <hw_channel name="tile_7.ahb0"/>
+    <hw_channel name="tile_7.dnp"/>
+    <hw_channel name="tile_6.dnp"/>
+    <chbuf name="tile_6.dxm"/>
+  </writepath>
+
+</architecture>
\ No newline at end of file