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diff --git a/dol/src/dol/visitor/hdsd/scd/fsm/scd_sts_base.h b/dol/src/dol/visitor/hdsd/scd/fsm/scd_sts_base.h
new file mode 100644
index 0000000..05c1e8d
--- /dev/null
+++ b/dol/src/dol/visitor/hdsd/scd/fsm/scd_sts_base.h
@@ -0,0 +1,101 @@
+#ifndef SCD_STS_BASE_H
+#define SCD_STS_BASE_H
+
+#include "scd_simulator.h"
+#include "scd_out_connector.h"
+#include "scd_command_writer.h"
+#include "scd_command_reader.h"
+#include "fsm/scd_cont_state.h"
+
+
+/* forward declaration */
+class scd_cont_man_slave;
+
+
+/**
+ * Base class for all control slave states.
+ */
+class scd_sts_base : public scd_cont_state
+{
+public:
+    /**
+     * Constructor.
+     * \param sim the simulation environment
+     * \param fsm the FSM of this state
+     */
+    scd_sts_base(scd_simulator& sim, scd_cont_man_slave& fsm);
+
+    virtual ~scd_sts_base() {}
+
+    /**
+     * Signalizes the state, that a failed message has been received
+     * from the master.
+     */
+    virtual void set_failed();
+
+    /**
+     * Signalizes the state, that a time_req message has been received
+     * from the master.
+     */
+    virtual void recv_time_req();
+
+    /**
+     * Signalizes the state, that a time_nack message has been received
+     * from the master.
+     */
+    virtual void recv_time_nack() {}
+
+    /**
+     * Signalizes the state, that a time message has been received
+     * from the master.
+     */
+    virtual void recv_time(const sc_core::sc_time& time);
+
+    /**
+     * Signalizes the state, that a term_req message has been received
+     * from the master.
+     */
+    virtual void recv_term_req();
+
+    /**
+     * Signalizes the state, that a term_nack message has been received
+     * from the master.
+     */
+    virtual void recv_term_nack() {}
+
+    /**
+     * Signalizes the state, that a term message has been received
+     * from the master.
+     */
+    virtual void recv_term();
+
+    /* scd_cont_fsm_if */
+    void set_busy() {}
+    void set_idle(const sc_core::sc_time& time) {}
+    void set_done() {}
+    void set_fail();
+    void process() {}
+    bool active() const;
+    bool busy() const;
+    bool failed() const;
+    bool advance_time() const;
+    const sc_core::sc_time& get_time_step();
+
+protected:
+    scd_cont_man_slave& _fsm;
+    scd_command_writer& _writer;
+    scd_command_reader& _reader;
+    scd_out_connector& _connector;
+    scd_cont_state& _st_init;
+    scd_cont_state& _st_busy;
+    scd_cont_state& _st_idle;
+    scd_cont_state& _st_done;
+    scd_cont_state& _st_time_ack;
+    scd_cont_state& _st_time;
+    scd_cont_state& _st_term_ack;
+    scd_cont_state& _st_terminated;
+    scd_cont_state& _st_fail;
+    scd_cont_state& _st_failed;
+};
+
+#endif